mirror of https://github.com/VLSIDA/OpenRAM.git
Move precharge vdd pin to left edge.
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@ -67,14 +67,14 @@ class precharge(pgate.pgate):
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vdd_pos = vector(pmos_pin.cx(), vdd_position.y + 0.5*self.m1_width)
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self.add_path("metal1", [pmos_pin.uc(), vdd_pos])
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# Always drop to M1
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# Add the M1->M2->M3 stack at the left edge
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=vdd_pos)
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offset=vdd_pos.scale(0,1))
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self.add_via_center(layers=("metal2", "via2", "metal3"),
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offset=vdd_pos)
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offset=vdd_pos.scale(0,1))
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self.add_layout_pin_rect_center(text="vdd",
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layer="metal3",
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offset=vdd_pos)
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offset=vdd_pos.scale(0,1))
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def add_ptx(self):
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