mirror of https://github.com/VLSIDA/OpenRAM.git
Move bank select below row decoder, col mux, or col decoder.
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85b7b73903
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875eb94a34
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@ -421,8 +421,11 @@ class bank(design.design):
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return
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x_off = -(self.row_decoder.width + self.central_bus_width + self.wordline_driver.width)
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# extra space to allow vias
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y_off = self.min_y_offset + 2*self.supply_rail_pitch + self.m1_space
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if self.col_addr_size > 0:
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y_off = min(self.col_decoder_inst.by(), self.col_mux_array_inst.by())
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else:
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y_off = self.row_decoder_inst.by()
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y_off -= (self.bank_select.height + drc["well_to_well"])
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self.bank_select_pos = vector(x_off,y_off)
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self.bank_select_inst = self.add_inst(name="bank_select",
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mod=self.bank_select,
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@ -466,11 +469,7 @@ class bank(design.design):
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def route_bank_select(self):
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""" Route the bank select logic. """
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for input_name in self.input_control_signals+["bank_sel"]:
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in_pos = self.bank_select_inst.get_pin(input_name).lc()
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self.add_layout_pin_segment_center(text=input_name,
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layer="metal3",
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start=vector(self.left_gnd_x_offset,in_pos.y),
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end=in_pos)
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self.copy_layout_pin(self.bank_select_inst, input_name)
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for gated_name in self.control_signals:
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# Connect the inverter output to the central bus
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