mirror of https://github.com/VLSIDA/OpenRAM.git
Remove carriage returns form python files
This commit is contained in:
Matt Guthaus
parent
abacf6a2d0
commit
34736b7b3f
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@ -1,115 +1,115 @@
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import gdsMill
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import tech
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import globals
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import math
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import debug
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import datetime
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from collections import defaultdict
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class lef:
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"""
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SRAM LEF Class open GDS file, read pins information, obstruction
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and write them to LEF file
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"""
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def __init__(self,layers):
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# LEF db units per micron
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self.lef_units = 1000
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# These are the layers of the obstructions
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self.lef_layers = layers
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def lef_write(self, lef_name):
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"""Write the entire lef of the object to the file."""
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debug.info(3, "Writing to {0}".format(lef_name))
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self.indent = "" # To maintain the indent level easily
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self.lef = open(lef_name,"w")
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self.lef_write_header()
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for pin in self.pins:
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self.lef_write_pin(pin)
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self.lef_write_obstructions()
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self.lef_write_footer()
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self.lef.close()
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def lef_write_header(self):
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""" Header of LEF file """
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self.lef.write("VERSION 5.4 ;\n")
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self.lef.write("NAMESCASESENSITIVE ON ;\n")
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self.lef.write("BUSBITCHARS \"[]\" ;\n")
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self.lef.write("DIVIDERCHAR \"/\" ;\n")
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self.lef.write("UNITS\n")
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self.lef.write(" DATABASE MICRONS {0} ;\n".format(self.lef_units))
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self.lef.write("END UNITS\n")
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self.lef.write("SITE MacroSite\n")
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self.indent += " "
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self.lef.write("{0}CLASS Core ;\n".format(self.indent))
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self.lef.write("{0}SIZE {1} by {2} ;\n".format(self.indent,
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self.lef_units*self.width,
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self.lef_units*self.height))
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self.indent = self.indent[:-3]
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self.lef.write("END MacroSite\n")
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self.lef.write("{0}MACRO {1}\n".format(self.indent,self.name))
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self.indent += " "
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self.lef.write("{0}CLASS BLOCK ;\n".format(self.indent))
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self.lef.write("{0}SIZE {1} BY {2} ;\n" .format(self.indent,
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self.lef_units*self.width,
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self.lef_units*self.height))
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self.lef.write("{0}SYMMETRY X Y R90 ;\n".format(self.indent))
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self.lef.write("{0}SITE MacroSite ;\n".format(self.indent))
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def lef_write_footer(self):
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self.lef.write("{0}END {1}\n".format(self.indent,self.name))
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self.indent = self.indent[:-3]
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self.lef.write("END LIBRARY\n")
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def lef_write_pin(self, name):
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pin_dir = self.get_pin_dir(name)
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pin_type = self.get_pin_type(name)
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self.lef.write("{0}PIN {1}\n".format(self.indent,name))
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self.indent += " "
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self.lef.write("{0}DIRECTION {1} ;\n".format(self.indent,pin_dir))
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if pin_type in ["POWER","GROUND"]:
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self.lef.write("{0}USE {1} ; \n".format(self.indent,pin_type))
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self.lef.write("{0}SHAPE ABUTMENT ; \n".format(self.indent))
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self.lef.write("{0}PORT\n".format(self.indent))
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self.indent += " "
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# We could sort these together to minimize different layer sections, but meh.
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pin_list = self.get_pins(name)
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for pin in pin_list:
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self.lef.write("{0}LAYER {1} ;\n".format(self.indent,pin.layer))
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self.lef_write_rect(pin.rect)
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# End the PORT
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self.indent = self.indent[:-3]
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self.lef.write("{0}END\n".format(self.indent))
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# End the PIN
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self.indent = self.indent[:-3]
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self.lef.write("{0}END {1}\n".format(self.indent,name))
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def lef_write_obstructions(self):
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""" Write all the obstructions on each layer """
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self.lef.write("{0}OBS\n".format(self.indent))
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for layer in self.lef_layers:
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self.lef.write("{0}LAYER {1} ;\n".format(self.indent,layer))
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self.indent += " "
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blockages = self.get_blockages(layer,True)
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for b in blockages:
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self.lef_write_rect(b)
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self.indent = self.indent[:-3]
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self.lef.write("{0}END\n".format(self.indent))
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def lef_write_rect(self, rect):
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""" Write a LEF rectangle """
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self.lef.write("{0}RECT ".format(self.indent))
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for item in rect:
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self.lef.write(" {0} {1}".format(self.lef_units*item[0], self.lef_units*item[1]))
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self.lef.write(" ;\n")
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import gdsMill
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import tech
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import globals
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import math
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import debug
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import datetime
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from collections import defaultdict
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class lef:
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"""
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SRAM LEF Class open GDS file, read pins information, obstruction
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and write them to LEF file
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"""
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def __init__(self,layers):
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# LEF db units per micron
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self.lef_units = 1000
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# These are the layers of the obstructions
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self.lef_layers = layers
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def lef_write(self, lef_name):
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"""Write the entire lef of the object to the file."""
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debug.info(3, "Writing to {0}".format(lef_name))
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self.indent = "" # To maintain the indent level easily
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self.lef = open(lef_name,"w")
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self.lef_write_header()
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for pin in self.pins:
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self.lef_write_pin(pin)
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self.lef_write_obstructions()
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self.lef_write_footer()
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self.lef.close()
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def lef_write_header(self):
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""" Header of LEF file """
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self.lef.write("VERSION 5.4 ;\n")
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self.lef.write("NAMESCASESENSITIVE ON ;\n")
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self.lef.write("BUSBITCHARS \"[]\" ;\n")
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self.lef.write("DIVIDERCHAR \"/\" ;\n")
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self.lef.write("UNITS\n")
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self.lef.write(" DATABASE MICRONS {0} ;\n".format(self.lef_units))
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self.lef.write("END UNITS\n")
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self.lef.write("SITE MacroSite\n")
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self.indent += " "
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self.lef.write("{0}CLASS Core ;\n".format(self.indent))
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self.lef.write("{0}SIZE {1} by {2} ;\n".format(self.indent,
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self.lef_units*self.width,
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self.lef_units*self.height))
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self.indent = self.indent[:-3]
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self.lef.write("END MacroSite\n")
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self.lef.write("{0}MACRO {1}\n".format(self.indent,self.name))
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self.indent += " "
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self.lef.write("{0}CLASS BLOCK ;\n".format(self.indent))
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self.lef.write("{0}SIZE {1} BY {2} ;\n" .format(self.indent,
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self.lef_units*self.width,
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self.lef_units*self.height))
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self.lef.write("{0}SYMMETRY X Y R90 ;\n".format(self.indent))
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self.lef.write("{0}SITE MacroSite ;\n".format(self.indent))
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def lef_write_footer(self):
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self.lef.write("{0}END {1}\n".format(self.indent,self.name))
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self.indent = self.indent[:-3]
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self.lef.write("END LIBRARY\n")
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def lef_write_pin(self, name):
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pin_dir = self.get_pin_dir(name)
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pin_type = self.get_pin_type(name)
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self.lef.write("{0}PIN {1}\n".format(self.indent,name))
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self.indent += " "
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self.lef.write("{0}DIRECTION {1} ;\n".format(self.indent,pin_dir))
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if pin_type in ["POWER","GROUND"]:
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self.lef.write("{0}USE {1} ; \n".format(self.indent,pin_type))
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self.lef.write("{0}SHAPE ABUTMENT ; \n".format(self.indent))
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self.lef.write("{0}PORT\n".format(self.indent))
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self.indent += " "
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# We could sort these together to minimize different layer sections, but meh.
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pin_list = self.get_pins(name)
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for pin in pin_list:
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self.lef.write("{0}LAYER {1} ;\n".format(self.indent,pin.layer))
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self.lef_write_rect(pin.rect)
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# End the PORT
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self.indent = self.indent[:-3]
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self.lef.write("{0}END\n".format(self.indent))
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# End the PIN
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self.indent = self.indent[:-3]
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self.lef.write("{0}END {1}\n".format(self.indent,name))
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def lef_write_obstructions(self):
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""" Write all the obstructions on each layer """
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self.lef.write("{0}OBS\n".format(self.indent))
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for layer in self.lef_layers:
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self.lef.write("{0}LAYER {1} ;\n".format(self.indent,layer))
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self.indent += " "
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blockages = self.get_blockages(layer,True)
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for b in blockages:
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self.lef_write_rect(b)
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self.indent = self.indent[:-3]
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self.lef.write("{0}END\n".format(self.indent))
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def lef_write_rect(self, rect):
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""" Write a LEF rectangle """
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self.lef.write("{0}RECT ".format(self.indent))
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for item in rect:
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self.lef.write(" {0} {1}".format(self.lef_units*item[0], self.lef_units*item[1]))
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self.lef.write(" ;\n")
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@ -1,202 +1,202 @@
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import debug
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import design
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from tech import drc, spice
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from vector import vector
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from globals import OPTS
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class bitcell_array(design.design):
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"""
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Creates a rows x cols array of memory cells. Assumes bit-lines
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and word line is connected by abutment.
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Connects the word lines and bit lines.
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"""
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def __init__(self, cols, rows, name="bitcell_array"):
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design.design.__init__(self, name)
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debug.info(1, "Creating {0} {1} x {2}".format(self.name, rows, cols))
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self.column_size = cols
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self.row_size = rows
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from importlib import reload
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c = reload(__import__(OPTS.bitcell))
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self.mod_bitcell = getattr(c, OPTS.bitcell)
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self.cell = self.mod_bitcell()
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self.add_mod(self.cell)
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# We increase it by a well enclosure so the precharges don't overlap our wells
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self.height = self.row_size*self.cell.height + drc["well_enclosure_active"] + self.m1_width
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self.width = self.column_size*self.cell.width + self.m1_width
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self.add_pins()
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self.create_layout()
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self.add_layout_pins()
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# We don't offset this because we need to align
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# the replica bitcell in the control logic
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#self.offset_all_coordinates()
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self.DRC_LVS()
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def add_pins(self):
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row_list = self.cell.list_row_pins()
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column_list = self.cell.list_all_column_pins()
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for col in range(self.column_size):
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for cell_column in column_list:
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self.add_pin(cell_column+"[{0}]".format(col))
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for row in range(self.row_size):
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for cell_row in row_list:
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self.add_pin(cell_row+"[{0}]".format(row))
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self.add_pin("vdd")
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self.add_pin("gnd")
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def create_layout(self):
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xoffset = 0.0
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self.cell_inst = {}
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for col in range(self.column_size):
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yoffset = 0.0
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for row in range(self.row_size):
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name = "bit_r{0}_c{1}".format(row, col)
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if row % 2:
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tempy = yoffset + self.cell.height
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dir_key = "MX"
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else:
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tempy = yoffset
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dir_key = ""
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self.cell_inst[row,col]=self.add_inst(name=name,
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mod=self.cell,
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offset=[xoffset, tempy],
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mirror=dir_key)
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self.connect_inst(self.cell.list_bitcell_pins(col, row))
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yoffset += self.cell.height
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xoffset += self.cell.width
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def add_layout_pins(self):
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""" Add the layout pins """
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row_list = self.cell.list_row_pins()
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column_list = self.cell.list_all_column_pins()
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offset = vector(0.0, 0.0)
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for col in range(self.column_size):
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for cell_column in column_list:
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bl_pin = self.cell_inst[0,col].get_pin(cell_column)
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self.add_layout_pin(text=cell_column+"[{0}]".format(col),
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layer="metal2",
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offset=bl_pin.ll(),
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width=bl_pin.width(),
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height=self.height)
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# increments to the next column width
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offset.x += self.cell.width
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offset.x = 0.0
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for row in range(self.row_size):
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for cell_row in row_list:
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wl_pin = self.cell_inst[row,0].get_pin(cell_row)
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self.add_layout_pin(text=cell_row+"[{0}]".format(row),
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layer="metal1",
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offset=wl_pin.ll(),
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width=self.width,
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height=wl_pin.height())
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# increments to the next row height
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offset.y += self.cell.height
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# For every second row and column, add a via for vdd
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for row in range(self.row_size):
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for col in range(self.column_size):
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inst = self.cell_inst[row,col]
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for vdd_pin in inst.get_pins("vdd"):
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# Drop to M1 if needed
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if vdd_pin.layer == "metal1":
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=vdd_pin.center(),
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rotate=90)
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# Always drop to M2
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self.add_via_center(layers=("metal2", "via2", "metal3"),
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offset=vdd_pin.center())
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self.add_layout_pin_rect_center(text="vdd",
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layer="metal3",
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offset=vdd_pin.center())
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# For every second row and column (+1), add a via for gnd
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for row in range(self.row_size):
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for col in range(self.column_size):
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inst = self.cell_inst[row,col]
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for gnd_pin in inst.get_pins("gnd"):
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# Drop to M1 if needed
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if gnd_pin.layer == "metal1":
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=gnd_pin.center(),
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rotate=90)
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# Always drop to M2
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self.add_via_center(layers=("metal2", "via2", "metal3"),
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offset=gnd_pin.center())
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self.add_layout_pin_rect_center(text="gnd",
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layer="metal3",
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offset=gnd_pin.center())
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def analytical_delay(self, slew, load=0):
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from tech import drc
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wl_wire = self.gen_wl_wire()
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wl_wire.return_delay_over_wire(slew)
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wl_to_cell_delay = wl_wire.return_delay_over_wire(slew)
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# hypothetical delay from cell to bl end without sense amp
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bl_wire = self.gen_bl_wire()
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cell_load = 2 * bl_wire.return_input_cap() # we ingore the wire r
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# hence just use the whole c
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bl_swing = 0.1
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cell_delay = self.cell.analytical_delay(wl_to_cell_delay.slew, cell_load, swing = bl_swing)
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#we do not consider the delay over the wire for now
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return self.return_delay(cell_delay.delay+wl_to_cell_delay.delay,
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wl_to_cell_delay.slew)
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def analytical_power(self, proc, vdd, temp, load):
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"""Power of Bitcell array and bitline in nW."""
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from tech import drc
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# Dynamic Power from Bitline
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bl_wire = self.gen_bl_wire()
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cell_load = 2 * bl_wire.return_input_cap()
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bl_swing = 0.1 #This should probably be defined in the tech file or input
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freq = spice["default_event_rate"]
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bitline_dynamic = bl_swing*cell_load*vdd*vdd*freq #not sure if calculation is correct
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#Calculate the bitcell power which currently only includes leakage
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cell_power = self.cell.analytical_power(proc, vdd, temp, load)
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#Leakage power grows with entire array and bitlines.
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total_power = self.return_power(cell_power.dynamic + bitline_dynamic * self.column_size,
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cell_power.leakage * self.column_size * self.row_size)
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return total_power
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def gen_wl_wire(self):
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wl_wire = self.generate_rc_net(int(self.column_size), self.width, drc["minwidth_metal1"])
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wl_wire.wire_c = 2*spice["min_tx_gate_c"] + wl_wire.wire_c # 2 access tx gate per cell
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return wl_wire
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def gen_bl_wire(self):
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bl_pos = 0
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bl_wire = self.generate_rc_net(int(self.row_size-bl_pos), self.height, drc["minwidth_metal1"])
|
||||
bl_wire.wire_c =spice["min_tx_drain_c"] + bl_wire.wire_c # 1 access tx d/s per cell
|
||||
return bl_wire
|
||||
|
||||
def output_load(self, bl_pos=0):
|
||||
bl_wire = self.gen_bl_wire()
|
||||
return bl_wire.wire_c # sense amp only need to charge small portion of the bl
|
||||
# set as one segment for now
|
||||
|
||||
def input_load(self):
|
||||
wl_wire = self.gen_wl_wire()
|
||||
return wl_wire.return_input_cap()
|
||||
import debug
|
||||
import design
|
||||
from tech import drc, spice
|
||||
from vector import vector
|
||||
from globals import OPTS
|
||||
|
||||
|
||||
|
||||
class bitcell_array(design.design):
|
||||
"""
|
||||
Creates a rows x cols array of memory cells. Assumes bit-lines
|
||||
and word line is connected by abutment.
|
||||
Connects the word lines and bit lines.
|
||||
"""
|
||||
|
||||
def __init__(self, cols, rows, name="bitcell_array"):
|
||||
design.design.__init__(self, name)
|
||||
debug.info(1, "Creating {0} {1} x {2}".format(self.name, rows, cols))
|
||||
|
||||
|
||||
self.column_size = cols
|
||||
self.row_size = rows
|
||||
|
||||
from importlib import reload
|
||||
c = reload(__import__(OPTS.bitcell))
|
||||
self.mod_bitcell = getattr(c, OPTS.bitcell)
|
||||
self.cell = self.mod_bitcell()
|
||||
self.add_mod(self.cell)
|
||||
|
||||
# We increase it by a well enclosure so the precharges don't overlap our wells
|
||||
self.height = self.row_size*self.cell.height + drc["well_enclosure_active"] + self.m1_width
|
||||
self.width = self.column_size*self.cell.width + self.m1_width
|
||||
|
||||
self.add_pins()
|
||||
self.create_layout()
|
||||
self.add_layout_pins()
|
||||
|
||||
# We don't offset this because we need to align
|
||||
# the replica bitcell in the control logic
|
||||
#self.offset_all_coordinates()
|
||||
|
||||
self.DRC_LVS()
|
||||
|
||||
def add_pins(self):
|
||||
row_list = self.cell.list_row_pins()
|
||||
column_list = self.cell.list_all_column_pins()
|
||||
for col in range(self.column_size):
|
||||
for cell_column in column_list:
|
||||
self.add_pin(cell_column+"[{0}]".format(col))
|
||||
for row in range(self.row_size):
|
||||
for cell_row in row_list:
|
||||
self.add_pin(cell_row+"[{0}]".format(row))
|
||||
self.add_pin("vdd")
|
||||
self.add_pin("gnd")
|
||||
|
||||
def create_layout(self):
|
||||
xoffset = 0.0
|
||||
self.cell_inst = {}
|
||||
for col in range(self.column_size):
|
||||
yoffset = 0.0
|
||||
for row in range(self.row_size):
|
||||
name = "bit_r{0}_c{1}".format(row, col)
|
||||
|
||||
if row % 2:
|
||||
tempy = yoffset + self.cell.height
|
||||
dir_key = "MX"
|
||||
else:
|
||||
tempy = yoffset
|
||||
dir_key = ""
|
||||
|
||||
self.cell_inst[row,col]=self.add_inst(name=name,
|
||||
mod=self.cell,
|
||||
offset=[xoffset, tempy],
|
||||
mirror=dir_key)
|
||||
self.connect_inst(self.cell.list_bitcell_pins(col, row))
|
||||
|
||||
yoffset += self.cell.height
|
||||
xoffset += self.cell.width
|
||||
|
||||
|
||||
def add_layout_pins(self):
|
||||
""" Add the layout pins """
|
||||
|
||||
row_list = self.cell.list_row_pins()
|
||||
column_list = self.cell.list_all_column_pins()
|
||||
|
||||
offset = vector(0.0, 0.0)
|
||||
for col in range(self.column_size):
|
||||
for cell_column in column_list:
|
||||
bl_pin = self.cell_inst[0,col].get_pin(cell_column)
|
||||
self.add_layout_pin(text=cell_column+"[{0}]".format(col),
|
||||
layer="metal2",
|
||||
offset=bl_pin.ll(),
|
||||
width=bl_pin.width(),
|
||||
height=self.height)
|
||||
|
||||
# increments to the next column width
|
||||
offset.x += self.cell.width
|
||||
|
||||
offset.x = 0.0
|
||||
for row in range(self.row_size):
|
||||
for cell_row in row_list:
|
||||
wl_pin = self.cell_inst[row,0].get_pin(cell_row)
|
||||
self.add_layout_pin(text=cell_row+"[{0}]".format(row),
|
||||
layer="metal1",
|
||||
offset=wl_pin.ll(),
|
||||
width=self.width,
|
||||
height=wl_pin.height())
|
||||
|
||||
# increments to the next row height
|
||||
offset.y += self.cell.height
|
||||
|
||||
# For every second row and column, add a via for vdd
|
||||
for row in range(self.row_size):
|
||||
for col in range(self.column_size):
|
||||
inst = self.cell_inst[row,col]
|
||||
for vdd_pin in inst.get_pins("vdd"):
|
||||
# Drop to M1 if needed
|
||||
if vdd_pin.layer == "metal1":
|
||||
self.add_via_center(layers=("metal1", "via1", "metal2"),
|
||||
offset=vdd_pin.center(),
|
||||
rotate=90)
|
||||
# Always drop to M2
|
||||
self.add_via_center(layers=("metal2", "via2", "metal3"),
|
||||
offset=vdd_pin.center())
|
||||
self.add_layout_pin_rect_center(text="vdd",
|
||||
layer="metal3",
|
||||
offset=vdd_pin.center())
|
||||
|
||||
|
||||
# For every second row and column (+1), add a via for gnd
|
||||
for row in range(self.row_size):
|
||||
for col in range(self.column_size):
|
||||
inst = self.cell_inst[row,col]
|
||||
for gnd_pin in inst.get_pins("gnd"):
|
||||
# Drop to M1 if needed
|
||||
if gnd_pin.layer == "metal1":
|
||||
self.add_via_center(layers=("metal1", "via1", "metal2"),
|
||||
offset=gnd_pin.center(),
|
||||
rotate=90)
|
||||
# Always drop to M2
|
||||
self.add_via_center(layers=("metal2", "via2", "metal3"),
|
||||
offset=gnd_pin.center())
|
||||
self.add_layout_pin_rect_center(text="gnd",
|
||||
layer="metal3",
|
||||
offset=gnd_pin.center())
|
||||
|
||||
def analytical_delay(self, slew, load=0):
|
||||
from tech import drc
|
||||
wl_wire = self.gen_wl_wire()
|
||||
wl_wire.return_delay_over_wire(slew)
|
||||
|
||||
wl_to_cell_delay = wl_wire.return_delay_over_wire(slew)
|
||||
# hypothetical delay from cell to bl end without sense amp
|
||||
bl_wire = self.gen_bl_wire()
|
||||
cell_load = 2 * bl_wire.return_input_cap() # we ingore the wire r
|
||||
# hence just use the whole c
|
||||
bl_swing = 0.1
|
||||
cell_delay = self.cell.analytical_delay(wl_to_cell_delay.slew, cell_load, swing = bl_swing)
|
||||
|
||||
#we do not consider the delay over the wire for now
|
||||
return self.return_delay(cell_delay.delay+wl_to_cell_delay.delay,
|
||||
wl_to_cell_delay.slew)
|
||||
|
||||
def analytical_power(self, proc, vdd, temp, load):
|
||||
"""Power of Bitcell array and bitline in nW."""
|
||||
from tech import drc
|
||||
|
||||
# Dynamic Power from Bitline
|
||||
bl_wire = self.gen_bl_wire()
|
||||
cell_load = 2 * bl_wire.return_input_cap()
|
||||
bl_swing = 0.1 #This should probably be defined in the tech file or input
|
||||
freq = spice["default_event_rate"]
|
||||
bitline_dynamic = bl_swing*cell_load*vdd*vdd*freq #not sure if calculation is correct
|
||||
|
||||
#Calculate the bitcell power which currently only includes leakage
|
||||
cell_power = self.cell.analytical_power(proc, vdd, temp, load)
|
||||
|
||||
#Leakage power grows with entire array and bitlines.
|
||||
total_power = self.return_power(cell_power.dynamic + bitline_dynamic * self.column_size,
|
||||
cell_power.leakage * self.column_size * self.row_size)
|
||||
return total_power
|
||||
|
||||
def gen_wl_wire(self):
|
||||
wl_wire = self.generate_rc_net(int(self.column_size), self.width, drc["minwidth_metal1"])
|
||||
wl_wire.wire_c = 2*spice["min_tx_gate_c"] + wl_wire.wire_c # 2 access tx gate per cell
|
||||
return wl_wire
|
||||
|
||||
def gen_bl_wire(self):
|
||||
bl_pos = 0
|
||||
bl_wire = self.generate_rc_net(int(self.row_size-bl_pos), self.height, drc["minwidth_metal1"])
|
||||
bl_wire.wire_c =spice["min_tx_drain_c"] + bl_wire.wire_c # 1 access tx d/s per cell
|
||||
return bl_wire
|
||||
|
||||
def output_load(self, bl_pos=0):
|
||||
bl_wire = self.gen_bl_wire()
|
||||
return bl_wire.wire_c # sense amp only need to charge small portion of the bl
|
||||
# set as one segment for now
|
||||
|
||||
def input_load(self):
|
||||
wl_wire = self.gen_wl_wire()
|
||||
return wl_wire.return_input_cap()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,78 +1,78 @@
|
|||
#!/usr/bin/env python2.7
|
||||
"""
|
||||
Run regresion tests on a parameterized bitcell
|
||||
"""
|
||||
|
||||
import unittest
|
||||
from testutils import header,openram_test
|
||||
import sys,os
|
||||
sys.path.append(os.path.join(sys.path[0],".."))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
import debug
|
||||
|
||||
OPTS = globals.OPTS
|
||||
|
||||
#@unittest.skip("SKIPPING 04_pbitcell_test")
|
||||
|
||||
|
||||
class pbitcell_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
|
||||
global verify
|
||||
import verify
|
||||
|
||||
import pbitcell
|
||||
import tech
|
||||
|
||||
debug.info(2, "Bitcell with 1 of each port: read/write, write, and read")
|
||||
tx = pbitcell.pbitcell(num_readwrite=1,num_write=1,num_read=1)
|
||||
self.local_check(tx)
|
||||
|
||||
debug.info(2, "Bitcell with 0 read/write ports")
|
||||
tx = pbitcell.pbitcell(num_readwrite=0,num_write=1,num_read=1)
|
||||
self.local_check(tx)
|
||||
|
||||
debug.info(2, "Bitcell with 0 write ports")
|
||||
tx = pbitcell.pbitcell(num_readwrite=1,num_write=0,num_read=1)
|
||||
self.local_check(tx)
|
||||
|
||||
debug.info(2, "Bitcell with 0 read ports")
|
||||
tx = pbitcell.pbitcell(num_readwrite=1,num_write=1,num_read=0)
|
||||
self.local_check(tx)
|
||||
|
||||
debug.info(2, "Bitcell with 0 read ports and 0 write ports")
|
||||
tx = pbitcell.pbitcell(num_readwrite=1,num_write=0,num_read=0)
|
||||
self.local_check(tx)
|
||||
|
||||
debug.info(2, "Bitcell with 2 of each port: read/write, write, and read")
|
||||
tx = pbitcell.pbitcell(num_readwrite=2,num_write=2,num_read=2)
|
||||
self.local_check(tx)
|
||||
|
||||
debug.info(2, "Bitcell with 0 read/write ports")
|
||||
tx = pbitcell.pbitcell(num_readwrite=0,num_write=2,num_read=2)
|
||||
self.local_check(tx)
|
||||
|
||||
debug.info(2, "Bitcell with 0 write ports")
|
||||
tx = pbitcell.pbitcell(num_readwrite=2,num_write=0,num_read=2)
|
||||
self.local_check(tx)
|
||||
|
||||
debug.info(2, "Bitcell with 0 read ports")
|
||||
tx = pbitcell.pbitcell(num_readwrite=2,num_write=2,num_read=0)
|
||||
self.local_check(tx)
|
||||
|
||||
debug.info(2, "Bitcell with 0 read ports and 0 write ports")
|
||||
tx = pbitcell.pbitcell(num_readwrite=2,num_write=0,num_read=0)
|
||||
self.local_check(tx)
|
||||
|
||||
globals.end_openram()
|
||||
|
||||
|
||||
|
||||
# instantiate a copy of the class to actually run the test
|
||||
if __name__ == "__main__":
|
||||
(OPTS, args) = globals.parse_args()
|
||||
del sys.argv[1:]
|
||||
header(__file__, OPTS.tech_name)
|
||||
unittest.main()
|
||||
#!/usr/bin/env python2.7
|
||||
"""
|
||||
Run regresion tests on a parameterized bitcell
|
||||
"""
|
||||
|
||||
import unittest
|
||||
from testutils import header,openram_test
|
||||
import sys,os
|
||||
sys.path.append(os.path.join(sys.path[0],".."))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
import debug
|
||||
|
||||
OPTS = globals.OPTS
|
||||
|
||||
#@unittest.skip("SKIPPING 04_pbitcell_test")
|
||||
|
||||
|
||||
class pbitcell_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
|
||||
global verify
|
||||
import verify
|
||||
|
||||
import pbitcell
|
||||
import tech
|
||||
|
||||
debug.info(2, "Bitcell with 1 of each port: read/write, write, and read")
|
||||
tx = pbitcell.pbitcell(num_readwrite=1,num_write=1,num_read=1)
|
||||
self.local_check(tx)
|
||||
|
||||
debug.info(2, "Bitcell with 0 read/write ports")
|
||||
tx = pbitcell.pbitcell(num_readwrite=0,num_write=1,num_read=1)
|
||||
self.local_check(tx)
|
||||
|
||||
debug.info(2, "Bitcell with 0 write ports")
|
||||
tx = pbitcell.pbitcell(num_readwrite=1,num_write=0,num_read=1)
|
||||
self.local_check(tx)
|
||||
|
||||
debug.info(2, "Bitcell with 0 read ports")
|
||||
tx = pbitcell.pbitcell(num_readwrite=1,num_write=1,num_read=0)
|
||||
self.local_check(tx)
|
||||
|
||||
debug.info(2, "Bitcell with 0 read ports and 0 write ports")
|
||||
tx = pbitcell.pbitcell(num_readwrite=1,num_write=0,num_read=0)
|
||||
self.local_check(tx)
|
||||
|
||||
debug.info(2, "Bitcell with 2 of each port: read/write, write, and read")
|
||||
tx = pbitcell.pbitcell(num_readwrite=2,num_write=2,num_read=2)
|
||||
self.local_check(tx)
|
||||
|
||||
debug.info(2, "Bitcell with 0 read/write ports")
|
||||
tx = pbitcell.pbitcell(num_readwrite=0,num_write=2,num_read=2)
|
||||
self.local_check(tx)
|
||||
|
||||
debug.info(2, "Bitcell with 0 write ports")
|
||||
tx = pbitcell.pbitcell(num_readwrite=2,num_write=0,num_read=2)
|
||||
self.local_check(tx)
|
||||
|
||||
debug.info(2, "Bitcell with 0 read ports")
|
||||
tx = pbitcell.pbitcell(num_readwrite=2,num_write=2,num_read=0)
|
||||
self.local_check(tx)
|
||||
|
||||
debug.info(2, "Bitcell with 0 read ports and 0 write ports")
|
||||
tx = pbitcell.pbitcell(num_readwrite=2,num_write=0,num_read=0)
|
||||
self.local_check(tx)
|
||||
|
||||
globals.end_openram()
|
||||
|
||||
|
||||
|
||||
# instantiate a copy of the class to actually run the test
|
||||
if __name__ == "__main__":
|
||||
(OPTS, args) = globals.parse_args()
|
||||
del sys.argv[1:]
|
||||
header(__file__, OPTS.tech_name)
|
||||
unittest.main()
|
||||
|
|
|
|||
Loading…
Reference in New Issue