mirror of https://github.com/VLSIDA/OpenRAM.git
Don't bring M2 rails over supply to allow supply connections.
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@ -50,6 +50,7 @@ class hierarchical_predecode(design.design):
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def setup_constraints(self):
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# use a conservative douple spacing just to get rid of annoying via DRCs
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self.m1_pitch = max(contact.m1m2.width,contact.m1m2.height) + max(self.m1_space, self.m2_space)
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self.m2_pitch = max(contact.m2m3.width,contact.m2m3.height) + max(self.m2_space,self.m3_space)
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# The rail offsets are indexed by the label
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@ -89,14 +90,14 @@ class hierarchical_predecode(design.design):
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if label.startswith("in"):
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self.add_layout_pin(text=label,
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layer="metal2",
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offset=vector(self.rails[label] - 0.5*self.m2_width, 0),
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offset=vector(self.rails[label] - 0.5*self.m1_width, self.m1_width),
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width=self.m2_width,
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height=self.height - 2*self.m2_space)
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height=self.height - 4*self.m1_width)
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else:
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self.add_rect(layer="metal2",
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offset=vector(self.rails[label] - 0.5*self.m2_width, 0),
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offset=vector(self.rails[label] - 0.5*self.m1_width, 2*self.m1_width),
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width=self.m2_width,
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height=self.height - 2*self.m2_space)
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height=self.height - 4*self.m1_width)
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def add_input_inverters(self):
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""" Create the input inverters to invert input signals for the decode stage. """
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