mirror of https://github.com/VLSIDA/OpenRAM.git
Fix missing vdd pins and fix routing between sense amp, bitcell array and column mux.
This commit is contained in:
Matt Guthaus
parent
248decd004
commit
d734c05b71
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@ -92,7 +92,8 @@ class bank(design.design):
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""" Create routing amoung the modules """
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self.route_central_bus()
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self.route_precharge_to_bitcell_array()
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self.route_sense_amp_to_bitcell_array()
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self.route_col_mux_to_bitcell_array()
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self.route_sense_amp_to_col_mux_or_bitcell_array()
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self.route_sense_amp_to_trigate()
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self.route_tri_gate_out()
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self.route_wordline_driver()
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@ -169,6 +170,9 @@ class bank(design.design):
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# A width on each side too
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self.central_bus_width = self.m2_pitch * self.num_control_lines + 2*self.m2_width
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# A space for wells or jogging m2
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self.m2_gap = max(2*drc["pwell_to_nwell"] + drc["well_enclosure_active"],
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2*self.m2_pitch)
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@ -231,9 +235,6 @@ class bank(design.design):
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temp.extend(["vdd", "gnd"])
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self.connect_inst(temp)
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# A space for wells or jogging m2
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self.m2_gap = max(2*drc["pwell_to_nwell"] + drc["well_enclosure_active"],
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2*self.m2_pitch)
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def add_precharge_array(self):
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""" Adding Precharge """
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@ -254,14 +255,12 @@ class bank(design.design):
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def add_column_mux_array(self):
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""" Adding Column Mux when words_per_row > 1 . """
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if self.col_addr_size > 0:
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# The m2 width is because the 6T cell may have vias on the boundary edge for
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# overlapping when making the array
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self.column_mux_height = self.column_mux_array.height + 0.5*self.m2_width
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self.column_mux_height = self.column_mux_array.height + self.m2_gap
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else:
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self.column_mux_height = 0
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return
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y_offset = self.column_mux_height
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y_offset = self.column_mux_height
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self.col_mux_array_inst=self.add_inst(name="column_mux_array",
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mod=self.column_mux_array,
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offset=vector(0,y_offset).scale(-1,-1))
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@ -425,7 +424,7 @@ class bank(design.design):
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x_off = -(self.row_decoder.width + self.central_bus_width + self.wordline_driver.width)
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# extra space to allow vias
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y_off = self.min_point + 2*self.supply_rail_pitch + self.m1_space
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y_off = self.min_y_offset + 2*self.supply_rail_pitch + self.m1_space
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self.bank_select_pos = vector(x_off,y_off)
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self.bank_select_inst = self.add_inst(name="bank_select",
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mod=self.bank_select,
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@ -459,9 +458,8 @@ class bank(design.design):
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for inst in top_instances:
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print inst.name
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# Column mux has no vdd
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if self.col_addr_size>0 and inst != self.col_mux_array_inst:
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if self.col_addr_size==0 or (self.col_addr_size>0 and inst != self.col_mux_array_inst):
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self.copy_layout_pin(inst, "vdd")
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# Precharge has no gnd
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if inst != self.precharge_array_inst:
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@ -583,20 +581,47 @@ class bank(design.design):
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vector(bitcell_br.x,yoffset), bitcell_br])
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def route_sense_amp_to_bitcell_array(self):
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""" Routing of BL and BR between pre-charge and bitcell array """
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def route_col_mux_to_bitcell_array(self):
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""" Routing of BL and BR between col mux and bitcell array """
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# Only do this if we have a column mux!
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if self.col_addr_size==0:
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return
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for i in range(self.num_cols):
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col_mux_bl = self.col_mux_array_inst.get_pin("bl[{}]".format(i)).uc()
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col_mux_br = self.col_mux_array_inst.get_pin("br[{}]".format(i)).uc()
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bitcell_bl = self.bitcell_array_inst.get_pin("bl[{}]".format(i)).bc()
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bitcell_br = self.bitcell_array_inst.get_pin("br[{}]".format(i)).bc()
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yoffset = 0.5*(col_mux_bl.y+bitcell_bl.y)
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self.add_path("metal2",[col_mux_bl, vector(col_mux_bl.x,yoffset),
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vector(bitcell_bl.x,yoffset), bitcell_bl])
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self.add_path("metal2",[col_mux_br, vector(col_mux_br.x,yoffset),
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vector(bitcell_br.x,yoffset), bitcell_br])
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def route_sense_amp_to_col_mux_or_bitcell_array(self):
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""" Routing of BL and BR between sense_amp and column mux or bitcell array """
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for i in range(self.word_size):
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sense_amp_bl = self.sense_amp_array_inst.get_pin("bl[{}]".format(i)).uc()
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sense_amp_br = self.sense_amp_array_inst.get_pin("br[{}]".format(i)).uc()
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bitcell_bl = self.bitcell_array_inst.get_pin("bl[{}]".format(i)).bc()
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bitcell_br = self.bitcell_array_inst.get_pin("br[{}]".format(i)).bc()
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yoffset = 0.5*(sense_amp_bl.y+bitcell_bl.y)
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if self.col_addr_size>0:
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# Sense amp is connected to the col mux
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connect_bl = self.col_mux_array_inst.get_pin("bl_out[{}]".format(i)).bc()
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connect_br = self.col_mux_array_inst.get_pin("br_out[{}]".format(i)).bc()
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else:
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# Sense amp is directly connected to the bitcell array
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connect_bl = self.bitcell_array_inst.get_pin("bl[{}]".format(i)).bc()
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connect_br = self.bitcell_array_inst.get_pin("br[{}]".format(i)).bc()
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yoffset = 0.5*(sense_amp_bl.y+connect_bl.y)
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self.add_path("metal2",[sense_amp_bl, vector(sense_amp_bl.x,yoffset),
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vector(bitcell_bl.x,yoffset), bitcell_bl])
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vector(connect_bl.x,yoffset), connect_bl])
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self.add_path("metal2",[sense_amp_br, vector(sense_amp_br.x,yoffset),
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vector(bitcell_br.x,yoffset), bitcell_br])
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vector(connect_br.x,yoffset), connect_br])
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def route_sense_amp_to_trigate(self):
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""" Routing of sense amp output to tri_gate input """
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@ -730,7 +755,8 @@ class bank(design.design):
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else:
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mid1_pos = vector(decode_out_pos.x + delta_offset + (self.num_col_addr_lines-i)*self.m2_pitch,decode_out_pos.y)
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mid2_pos = vector(mid1_pos.x,mux_addr_pos.y)
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self.add_wire(("metal1","via1","metal2"),[decode_out_pos, mid1_pos, mid2_pos, mux_addr_pos])
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#self.add_wire(("metal1","via1","metal2"),[decode_out_pos, mid1_pos, mid2_pos, mux_addr_pos])
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self.add_path("metal1",[decode_out_pos, mid1_pos, mid2_pos, mux_addr_pos])
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@ -747,7 +773,7 @@ class bank(design.design):
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wl_pin = self.bitcell_array_inst.get_pin(wl_name)
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self.add_label(text=wl_name,
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layer="metal1",
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offset=wl_pin.ll())
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offset=wl_pin.center())
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# Add the bitline names
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for i in range(self.num_cols):
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@ -757,10 +783,10 @@ class bank(design.design):
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br_pin = self.bitcell_array_inst.get_pin(br_name)
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self.add_label(text=bl_name,
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layer="metal2",
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offset=bl_pin.ll())
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offset=bl_pin.center())
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self.add_label(text=br_name,
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layer="metal2",
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offset=br_pin.ll())
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offset=br_pin.center())
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# Add the data output names to the sense amp output
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for i in range(self.word_size):
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@ -768,7 +794,16 @@ class bank(design.design):
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data_pin = self.sense_amp_array_inst.get_pin(data_name)
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self.add_label(text="sa_out[{}]".format(i),
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layer="metal3",
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offset=data_pin.ll())
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offset=data_pin.center())
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# Add labels on the decoder
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for i in range(self.word_size):
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data_name = "dec_out[{}]".format(i)
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pin_name = "in[{}]".format(i)
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data_pin = self.wordline_driver_inst.get_pin(pin_name)
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self.add_label(text=data_name,
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layer="metal1",
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offset=data_pin.center())
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def route_control_lines(self):
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