mirror of https://github.com/VLSIDA/OpenRAM.git
Move WL gnd contacts outside the cell for simplicity
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@ -42,7 +42,8 @@ class replica_bitline(design.design):
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#self.add_lvs_correspondence_points()
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self.width = self.rbl_inst.rx() - self.dc_inst.lx()
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# Plus a pitch for the WL contacts on the RBL
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self.width = self.rbl_inst.rx() - self.dc_inst.lx() + self.m1_pitch
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self.height = max(self.rbl_inst.uy(), self.dc_inst.uy())
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self.DRC_LVS()
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@ -140,9 +141,15 @@ class replica_bitline(design.design):
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for row in range(self.bitcell_loads):
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wl = "wl[{}]".format(row)
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pin = self.rbl_inst.get_pin(wl)
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# Route the connection to the right so that it doesn't interfere
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# with the cells
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pin_right = pin.rc()
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pin_extension = pin_right + vector(self.m1_pitch,0)
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if pin.layer != "metal1":
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continue
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self.add_power_pin("gnd", pin.rc())
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self.add_path("metal1", [pin_right, pin_extension])
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self.add_power_pin("gnd", pin_extension)
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def route_supplies(self):
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