mirror of https://github.com/VLSIDA/OpenRAM.git
Get rid of netgen error of undefined dlatch. Fix sp_read to find correct subckt name and pins.
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01244347c1
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2b839d34a3
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@ -97,8 +97,8 @@ class spice(verilog.verilog):
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for i in range(len(self.spice)):
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self.spice[i] = self.spice[i].rstrip(" \n")
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# find first subckt line in the file
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subckt = re.compile("^.subckt", re.IGNORECASE)
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# find the correct subckt line in the file
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subckt = re.compile("^.subckt {}".format(self.name), re.IGNORECASE)
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subckt_line = filter(subckt.search, self.spice)[0]
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# parses line into ports and remove subckt
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self.pins = subckt_line.split(" ")[2:]
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@ -1,10 +1,5 @@
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*master-slave flip-flop with both output and inverted ouput
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.SUBCKT ms_flop din dout dout_bar clk vdd gnd
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xmaster din mout mout_bar clk clk_bar vdd gnd dlatch
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xslave mout_bar dout_bar dout clk_bar clk_nn vdd gnd dlatch
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.ENDS flop
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.SUBCKT dlatch din dout dout_bar clk clk_bar vdd gnd
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*clk inverter
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mPff1 clk_bar clk vdd vdd PMOS_VTG W=180.0n L=50n m=1
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@ -27,3 +22,8 @@ mtmP2 int1 clk_bar dout vdd PMOS_VTG W=180.0n L=50n m=1
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mtmN2 int1 clk dout gnd NMOS_VTG W=90n L=50n m=1
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.ENDS dlatch
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.SUBCKT ms_flop din dout dout_bar clk vdd gnd
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xmaster din mout mout_bar clk clk_bar vdd gnd dlatch
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xslave mout_bar dout_bar dout clk_bar clk_nn vdd gnd dlatch
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.ENDS flop
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@ -1,10 +1,5 @@
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*master-slave flip-flop with both output and inverted ouput
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.subckt ms_flop din dout dout_bar clk vdd gnd
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xmaster din mout mout_bar clk clk_bar vdd gnd dlatch
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xslave mout_bar dout_bar dout clk_bar clk_nn vdd gnd dlatch
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.ends flop
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.subckt dlatch din dout dout_bar clk clk_bar vdd gnd
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*clk inverter
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mPff1 clk_bar clk vdd vdd p W=1.8u L=0.6u m=1
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@ -27,3 +22,8 @@ mtmP2 int1 clk_bar dout vdd p W=1.8u L=0.6u m=1
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mtmN2 int1 clk dout gnd n W=0.9u L=0.6u m=1
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.ends dlatch
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.subckt ms_flop din dout dout_bar clk vdd gnd
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xmaster din mout mout_bar clk clk_bar vdd gnd dlatch
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xslave mout_bar dout_bar dout clk_bar clk_nn vdd gnd dlatch
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.ends flop
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