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Changing function names in bitcell and pbitcell to better reflect what values they're returning. Editting function calls in bitcell_array and bank accordingly.

This commit is contained in:
Michael Timothy Grimes 2018-08-26 14:37:17 -07:00
parent b8ae21a52b
commit 8c73a26daa
4 changed files with 54 additions and 58 deletions
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21
compiler/modules/bank.py
View File

@ -187,16 +187,17 @@ class bank(design.design):
self.add_mod(self.bitcell_array)
# create arrays of bitline and bitline_bar names for read, write, or all ports
self.read_bl_list = self.bitcell.list_read_column_pins()
self.read_br_list = self.bitcell.list_read_bar_column_pins()
self.read_bl_list = self.bitcell.list_read_bl_names()
self.read_br_list = self.bitcell.list_read_br_names()
self.write_bl_list = self.bitcell.list_write_column_pins()
self.write_br_list = self.bitcell.list_write_bar_column_pins()
self.write_bl_list = self.bitcell.list_write_bl_names()
self.write_br_list = self.bitcell.list_write_br_names()
self.total_bl_list = self.bitcell.list_column_pins()
self.total_br_list = self.bitcell.list_column_bar_pins()
self.total_bl_list = self.bitcell.list_all_bl_names()
self.total_br_list = self.bitcell.list_all_br_names()
self.total_wl_list = self.bitcell.list_row_pins()
self.total_wl_list = self.bitcell.list_all_wl_names()
self.total_bitline_list = self.bitcell.list_all_bitline_names()
self.precharge_array = [None] * self.total_read
for k in range(self.total_read):
@ -239,13 +240,11 @@ class bank(design.design):
offset=vector(0,0))
temp = []
bl_list = self.bitcell.list_all_column_pins()
wl_list = self.bitcell.list_row_pins()
for col in range(self.num_cols):
for bitline in bl_list:
for bitline in self.total_bitline_list:
temp.append(bitline+"[{0}]".format(col))
for row in range(self.num_rows):
for wordline in wl_list:
for wordline in self.total_wl_list:
temp.append(wordline+"[{0}]".format(row))
temp.append("vdd")
temp.append("gnd")

42
compiler/modules/bitcell.py
View File

@ -44,56 +44,54 @@ class bitcell(design.design):
"vdd",
"gnd"]
return bitcell_pins
def list_row_pins(self):
""" Creates a list of all row pins (except for gnd and vdd) """
def list_all_wl_names(self):
""" Creates a list of all wordline pin names """
row_pins = ["wl"]
return row_pins
def list_read_row_pins(self):
""" Creates a list of row pins associated with read ports """
def list_read_wl_names(self):
""" Creates a list of wordline pin names associated with read ports """
row_pins = ["wl"]
return row_pins
def list_write_row_pins(self):
""" Creates a list of row pins associated with write ports """
def list_write_wl_names(self):
""" Creates a list of wordline pin names associated with write ports """
row_pins = ["wl"]
return row_pins
def list_all_column_pins(self):
""" Creates a list of all column pins (except for gnd and vdd) """
def list_all_bitline_names(self):
""" Creates a list of all bitline pin names (both bl and br) """
column_pins = ["bl", "br"]
return column_pins
def list_column_pins(self):
""" Creates a list of all column pins (except for gnd and vdd) """
def list_all_bl_names(self):
""" Creates a list of all bl pins names """
column_pins = ["bl"]
return column_pins
def list_column_bar_pins(self):
""" Creates a list of all column pins (except for gnd and vdd) """
def list_all_br_names(self):
""" Creates a list of all br pins names """
column_pins = ["br"]
return column_pins
def list_read_column_pins(self):
""" Creates a list of column pins associated with read ports """
def list_read_bl_names(self):
""" Creates a list of bl pin names associated with read ports """
column_pins = ["bl"]
return column_pins
def list_read_bar_column_pins(self):
""" Creates a list of column pins associated with read_bar ports """
def list_read_br_names(self):
""" Creates a list of br pin names associated with read ports """
column_pins = ["br"]
return column_pins
def list_write_column_pins(self):
""" Creates a list of column pins associated with write ports """
def list_write_bl_names(self):
""" Creates a list of bl pin names associated with write ports """
column_pins = ["bl"]
return column_pins
def list_write_bar_column_pins(self):
""" Creates a list of column pins asscociated with write_bar ports"""
def list_write_br_names(self):
""" Creates a list of br pin names asscociated with write ports"""
column_pins = ["br"]
return column_pins

8
compiler/modules/bitcell_array.py
View File

@ -42,8 +42,8 @@ class bitcell_array(design.design):
self.DRC_LVS()
def add_pins(self):
row_list = self.cell.list_row_pins()
column_list = self.cell.list_all_column_pins()
row_list = self.cell.list_all_wl_names()
column_list = self.cell.list_all_bitline_names()
for col in range(self.column_size):
for cell_column in column_list:
self.add_pin(cell_column+"[{0}]".format(col))
@ -81,8 +81,8 @@ class bitcell_array(design.design):
def add_layout_pins(self):
""" Add the layout pins """
row_list = self.cell.list_row_pins()
column_list = self.cell.list_all_column_pins()
row_list = self.cell.list_all_wl_names()
column_list = self.cell.list_all_bitline_names()
offset = vector(0.0, 0.0)
for col in range(self.column_size):

41
compiler/pgates/pbitcell.py
View File

@ -1055,10 +1055,9 @@ class pbitcell(pgate.pgate):
bitcell_pins.append("gnd")
return bitcell_pins
def list_row_pins(self):
""" Creates a list of all row pins (except for gnd and vdd) """
def list_all_wl_names(self):
""" Creates a list of all wordline pin names """
row_pins = []
for k in range(self.num_readwrite):
row_pins.append("rwwl{0}".format(k))
@ -1069,8 +1068,8 @@ class pbitcell(pgate.pgate):
return row_pins
def list_read_row_pins(self):
""" Creates a list of row pins associated with read ports """
def list_read_wl_names(self):
""" Creates a list of wordline pin names associated with read ports """
row_pins = []
for k in range(self.num_readwrite):
row_pins.append("rwwl{0}".format(k))
@ -1079,8 +1078,8 @@ class pbitcell(pgate.pgate):
return row_pins
def list_write_row_pins(self):
""" Creates a list of row pins associated with write ports """
def list_write_wl_names(self):
""" Creates a list of wordline pin names associated with write ports """
row_pins = []
for k in range(self.num_readwrite):
row_pins.append("rwwl{0}".format(k))
@ -1090,8 +1089,8 @@ class pbitcell(pgate.pgate):
return row_pins
def list_all_column_pins(self):
""" Creates a list of all bitline pins """
def list_all_bitline_names(self):
""" Creates a list of all bitline pin names (both bl and br) """
column_pins = []
for k in range(self.num_readwrite):
column_pins.append("rwbl{0}".format(k))
@ -1105,8 +1104,8 @@ class pbitcell(pgate.pgate):
return column_pins
def list_column_pins(self):
""" Creates a list of all bitline bar pins """
def list_all_bl_names(self):
""" Creates a list of all bl pins names """
column_pins = []
for k in range(self.num_readwrite):
column_pins.append("rwbl{0}".format(k))
@ -1117,8 +1116,8 @@ class pbitcell(pgate.pgate):
return column_pins
def list_column_bar_pins(self):
""" Creates a list of all bitline bar pins """
def list_all_br_names(self):
""" Creates a list of all br pins names """
column_pins = []
for k in range(self.num_readwrite):
column_pins.append("rwbl_bar{0}".format(k))
@ -1129,8 +1128,8 @@ class pbitcell(pgate.pgate):
return column_pins
def list_read_column_pins(self):
""" Creates a list of column pins associated with read ports """
def list_read_bl_names(self):
""" Creates a list of bl pin names associated with read ports """
column_pins = []
for k in range(self.num_readwrite):
column_pins.append("rwbl{0}".format(k))
@ -1139,8 +1138,8 @@ class pbitcell(pgate.pgate):
return column_pins
def list_read_bar_column_pins(self):
""" Creates a list of column pins associated with read_bar ports """
def list_read_br_names(self):
""" Creates a list of br pin names associated with read ports """
column_pins = []
for k in range(self.num_readwrite):
column_pins.append("rwbl_bar{0}".format(k))
@ -1149,8 +1148,8 @@ class pbitcell(pgate.pgate):
return column_pins
def list_write_column_pins(self):
""" Creates a list of column pins associated with write ports """
def list_write_bl_names(self):
""" Creates a list of bl pin names associated with write ports """
column_pins = []
for k in range(self.num_readwrite):
column_pins.append("rwbl{0}".format(k))
@ -1159,8 +1158,8 @@ class pbitcell(pgate.pgate):
return column_pins
def list_write_bar_column_pins(self):
""" Creates a list of column pins asscociated with write_bar ports"""
def list_write_br_names(self):
""" Creates a list of br pin names asscociated with write ports"""
column_pins = []
for k in range(self.num_readwrite):
column_pins.append("rwbl_bar{0}".format(k))