mirror of https://github.com/VLSIDA/OpenRAM.git
SCMOS library cells passing LVS (with property errors though). Permute must be enabled before compare, duh.
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@ -26,7 +26,7 @@ class library_drc_test(unittest.TestCase):
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drc_errors += 1
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debug.error("Missing GDS file: {}".format(gds_name))
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drc_errors += verify.run_drc(name, gds_name)
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self.assertEqual(drc_errors, 0)
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# fails if there are any DRC errors on any cells
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self.assertEqual(drc_errors, 0)
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globals.end_openram()
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@ -28,7 +28,7 @@ class library_lvs_test(unittest.TestCase):
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lvs_errors += 1
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debug.error("Missing SPICE file {}".format(gds_name))
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lvs_errors += verify.run_lvs(f, gds_name, sp_name)
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self.assertEqual(lvs_errors, 0)
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# fail if the error count is not zero
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self.assertEqual(lvs_errors, 0)
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globals.end_openram()
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@ -116,10 +116,10 @@ def write_netgen_script(cell_name, sp_name):
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#f.write("lvs {0}.spice {{{1} {0}}}\n".format(cell_name, sp_name))
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f.write("log file lvs.results\n")
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f.write("log start\n")
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f.write("permute default\n")
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f.write("compare hierarchical {0}{1}.spice {{{2} {1}}}\n".format(OPTS.openram_temp,
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cell_name,
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sp_name))
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f.write("permute\n")
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f.write("run converge\n")
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f.write("log end\n")
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f.write("quit\n")
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Binary file not shown.
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@ -1,6 +1,6 @@
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magic
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tech scmos
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timestamp 1516667113
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timestamp 1516668097
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<< nwell >>
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rect -3 100 37 137
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rect -3 -1 37 50
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@ -230,7 +230,7 @@ rect 0 0 34 201
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rlabel metal2 20 201 20 201 5 BR
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rlabel metal2 10 201 10 201 5 BL
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rlabel metal1 0 30 0 30 1 vdd
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rlabel metal1 0 23 0 23 3 en
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rlabel metal1 0 16 0 16 7 gnd
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rlabel metal2 15 0 15 0 1 din
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rlabel metal1 0 23 2 24 3 wen
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<< end >>
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