SCMOS library cells passing LVS (with property errors though). Permute must be enabled before compare, duh.

This commit is contained in:
Matt Guthaus 2018-01-22 17:14:39 -08:00
parent fb2ed1d46c
commit 2468f224d9
5 changed files with 5 additions and 5 deletions

View File

@ -26,7 +26,7 @@ class library_drc_test(unittest.TestCase):
drc_errors += 1
debug.error("Missing GDS file: {}".format(gds_name))
drc_errors += verify.run_drc(name, gds_name)
self.assertEqual(drc_errors, 0)
# fails if there are any DRC errors on any cells
self.assertEqual(drc_errors, 0)
globals.end_openram()

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@ -28,7 +28,7 @@ class library_lvs_test(unittest.TestCase):
lvs_errors += 1
debug.error("Missing SPICE file {}".format(gds_name))
lvs_errors += verify.run_lvs(f, gds_name, sp_name)
self.assertEqual(lvs_errors, 0)
# fail if the error count is not zero
self.assertEqual(lvs_errors, 0)
globals.end_openram()

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@ -116,10 +116,10 @@ def write_netgen_script(cell_name, sp_name):
#f.write("lvs {0}.spice {{{1} {0}}}\n".format(cell_name, sp_name))
f.write("log file lvs.results\n")
f.write("log start\n")
f.write("permute default\n")
f.write("compare hierarchical {0}{1}.spice {{{2} {1}}}\n".format(OPTS.openram_temp,
cell_name,
sp_name))
f.write("permute\n")
f.write("run converge\n")
f.write("log end\n")
f.write("quit\n")

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@ -1,6 +1,6 @@
magic
tech scmos
timestamp 1516667113
timestamp 1516668097
<< nwell >>
rect -3 100 37 137
rect -3 -1 37 50
@ -230,7 +230,7 @@ rect 0 0 34 201
rlabel metal2 20 201 20 201 5 BR
rlabel metal2 10 201 10 201 5 BL
rlabel metal1 0 30 0 30 1 vdd
rlabel metal1 0 23 0 23 3 en
rlabel metal1 0 16 0 16 7 gnd
rlabel metal2 15 0 15 0 1 din
rlabel metal1 0 23 2 24 3 wen
<< end >>