mirror of https://github.com/VLSIDA/OpenRAM.git
Added corner paramters to power functions. This commit does not compile (sorry)
This commit is contained in:
Hunter Nichols
parent
d4a0f48d4f
commit
beb7dad9bc
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@ -121,10 +121,10 @@ class design(hierarchy_spice.spice, hierarchy_layout.layout):
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text+=str(i)+",\n"
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return text
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def analytical_power(self, slew, load):
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def analytical_power(self, vdd, temp, load):
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""" Get total power of a module """
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#print "Getting power for ",self.name," module"
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total_module_power = 0
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for inst in self.insts:
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total_module_power += inst.mod.analytical_power(slew, load)
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total_module_power = self.return_power()
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# for inst in self.insts:
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# total_module_power += self.return_power()#inst.mod.analytical_power(vdd, temp, load)
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return total_module_power
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@ -215,7 +215,7 @@ class spice(verilog.verilog):
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def generate_rc_net(self,lump_num, wire_length, wire_width):
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return wire_spice_model(lump_num, wire_length, wire_width)
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def return_power(self, dynamic, leakage):
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def return_power(self, dynamic=0.0, leakage=0.0):
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return power_data(dynamic, leakage)
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class delay_data:
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@ -97,7 +97,7 @@ class control_logic(design.design):
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# GAP between main control and replica bitline
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self.replica_bitline_gap = 2*self.m2_pitch
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def add_modules(self):
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@ -691,7 +691,10 @@ class control_logic(design.design):
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def analytical_power(self, vdd, temp, load):
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#This has yet to be fully determined.
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print "Instances:"
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total_power = self.return_power() #empty power object
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for inst in self.insts:
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print inst.name," Instance"
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total_power += inst.mod.analytical_power(vdd, temp, load)
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#currently, only return flop array power
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return 0
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return total_power
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@ -27,8 +27,11 @@ class ms_flop(design.design):
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result = self.return_delay(spice["msflop_delay"], spice["msflop_slew"])
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return result
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def analytical_power(self, slew, load = 0.0):
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def analytical_power(self, vdd, temp, load):
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#Value taken from tech file.
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from tech import spice
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return spice["msflop_power"]
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return self.return_power()
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#return spice["msflop_power"]
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@ -135,5 +135,5 @@ class ms_flop_array(design.design):
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def analytical_delay(self, slew, load=0.0):
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return self.ms.analytical_delay(slew=slew, load=load)
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def analytical_power(self, slew, load):
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return self.columns * self.ms.analytical_power(slew=slew, load=load)
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# def analytical_power(self, vdd, temp, load):
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# return self.columns * self.ms.analytical_power(slew=slew, load=load)
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@ -344,3 +344,14 @@ class replica_bitline(design.design):
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height=pin.height(),
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width=pin.width())
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# def analytical_power(self, vdd, temp, load):
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# #This has yet to be fully determined.
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# print "Instances:"
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# total_power = 0
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# for inst in self.insts:
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# print inst.name," Instance"
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# #total_power += inst.mod.analytical_power(vdd, temp, load)
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# #currently, only return flop array power
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# return total_power
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@ -214,6 +214,6 @@ class pnand2(pgate.pgate):
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c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff
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return self.cal_delay_with_rc(r = r, c = c_para+load, slew = slew)
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def analytical_power(self, slew, load=0.0):
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def analytical_power(self, vdd, temp, load):
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#Adding a magic number until I can properly define this.
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return 1
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return self.return_power()
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@ -234,6 +234,6 @@ class pnand3(pgate.pgate):
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c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff
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return self.cal_delay_with_rc(r = r, c = c_para+load, slew = slew)
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def analytical_power(self, slew, load=0.0):
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def analytical_power(self, vdd, temp, load):
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#Adding a magic number until I can properly define this.
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return 2
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return self.return_power()
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@ -219,7 +219,8 @@ class pnor2(pgate.pgate):
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def input_load(self):
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return ((self.nmos_size+self.pmos_size)/parameter["min_tx_size"])*spice["min_tx_gate_c"]
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def analytical_delay(self, slew, load=0.0):
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def analytical_delay(self, vdd, temp, load):
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r = spice["min_tx_r"]/(self.nmos_size/parameter["min_tx_size"])
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c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff
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return self.cal_delay_with_rc(r = r, c = c_para+load, slew = slew)
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@ -76,254 +76,3 @@ cell (sram_2_16_1_freepdk45){
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dont_touch : true;
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area : 1756.7563625;
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bus(DATA){
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bus_type : DATA;
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direction : inout;
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max_capacitance : 1.6728;
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three_state : "!OEb & !clk";
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memory_write(){
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address : ADDR;
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clocked_on : clk;
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}
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memory_read(){
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address : ADDR;
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}
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pin(DATA[1:0]){
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internal_power(){
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when : "OEb & !clk";
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rise_power(scalar){
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values("0");
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}
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fall_power(scalar){
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values("0");
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}
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}
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timing(){
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timing_type : setup_rising;
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related_pin : "clk";
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rise_constraint(CONSTRAINT_TABLE) {
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values("0.009, 0.009, 0.009",\
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"0.009, 0.009, 0.009",\
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"0.009, 0.009, 0.009");
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}
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fall_constraint(CONSTRAINT_TABLE) {
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values("0.009, 0.009, 0.009",\
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"0.009, 0.009, 0.009",\
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"0.009, 0.009, 0.009");
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}
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}
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timing(){
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timing_type : hold_rising;
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related_pin : "clk";
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rise_constraint(CONSTRAINT_TABLE) {
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values("0.001, 0.001, 0.001",\
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"0.001, 0.001, 0.001",\
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"0.001, 0.001, 0.001");
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}
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fall_constraint(CONSTRAINT_TABLE) {
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values("0.001, 0.001, 0.001",\
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"0.001, 0.001, 0.001",\
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"0.001, 0.001, 0.001");
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}
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}
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internal_power(){
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when : "!OEb & !clk";
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rise_power(scalar){
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values("0");
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}
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fall_power(scalar){
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values("0");
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}
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}
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timing(){
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timing_sense : non_unate;
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related_pin : "clk";
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timing_type : falling_edge;
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cell_rise(CELL_TABLE) {
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values("0.167, 0.168, 0.177",\
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"0.167, 0.168, 0.177",\
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"0.167, 0.168, 0.177");
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}
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cell_fall(CELL_TABLE) {
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values("0.167, 0.168, 0.177",\
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"0.167, 0.168, 0.177",\
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"0.167, 0.168, 0.177");
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}
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rise_transition(CELL_TABLE) {
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values("0.006, 0.007, 0.018",\
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"0.006, 0.007, 0.018",\
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"0.006, 0.007, 0.018");
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}
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fall_transition(CELL_TABLE) {
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values("0.006, 0.007, 0.018",\
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"0.006, 0.007, 0.018",\
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"0.006, 0.007, 0.018");
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}
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}
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}
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}
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bus(ADDR){
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bus_type : ADDR;
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direction : input;
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capacitance : 0.2091;
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max_transition : 0.04;
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fanout_load : 1.000000;
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pin(ADDR[6:0]){
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timing(){
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timing_type : setup_rising;
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related_pin : "clk";
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rise_constraint(CONSTRAINT_TABLE) {
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values("0.009, 0.009, 0.009",\
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"0.009, 0.009, 0.009",\
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"0.009, 0.009, 0.009");
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}
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fall_constraint(CONSTRAINT_TABLE) {
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values("0.009, 0.009, 0.009",\
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"0.009, 0.009, 0.009",\
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"0.009, 0.009, 0.009");
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}
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}
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timing(){
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timing_type : hold_rising;
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related_pin : "clk";
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rise_constraint(CONSTRAINT_TABLE) {
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values("0.001, 0.001, 0.001",\
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"0.001, 0.001, 0.001",\
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"0.001, 0.001, 0.001");
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}
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fall_constraint(CONSTRAINT_TABLE) {
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values("0.001, 0.001, 0.001",\
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"0.001, 0.001, 0.001",\
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"0.001, 0.001, 0.001");
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}
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}
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}
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}
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pin(CSb){
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direction : input;
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capacitance : 0.2091;
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timing(){
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timing_type : setup_rising;
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related_pin : "clk";
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rise_constraint(CONSTRAINT_TABLE) {
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values("0.009, 0.009, 0.009",\
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"0.009, 0.009, 0.009",\
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"0.009, 0.009, 0.009");
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}
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fall_constraint(CONSTRAINT_TABLE) {
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values("0.009, 0.009, 0.009",\
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"0.009, 0.009, 0.009",\
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"0.009, 0.009, 0.009");
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}
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}
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timing(){
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timing_type : hold_rising;
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related_pin : "clk";
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rise_constraint(CONSTRAINT_TABLE) {
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values("0.001, 0.001, 0.001",\
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"0.001, 0.001, 0.001",\
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"0.001, 0.001, 0.001");
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}
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fall_constraint(CONSTRAINT_TABLE) {
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values("0.001, 0.001, 0.001",\
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"0.001, 0.001, 0.001",\
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"0.001, 0.001, 0.001");
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}
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}
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}
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pin(OEb){
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direction : input;
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capacitance : 0.2091;
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timing(){
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timing_type : setup_rising;
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related_pin : "clk";
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rise_constraint(CONSTRAINT_TABLE) {
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values("0.009, 0.009, 0.009",\
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"0.009, 0.009, 0.009",\
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"0.009, 0.009, 0.009");
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}
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fall_constraint(CONSTRAINT_TABLE) {
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values("0.009, 0.009, 0.009",\
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"0.009, 0.009, 0.009",\
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"0.009, 0.009, 0.009");
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}
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}
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timing(){
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timing_type : hold_rising;
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related_pin : "clk";
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rise_constraint(CONSTRAINT_TABLE) {
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values("0.001, 0.001, 0.001",\
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"0.001, 0.001, 0.001",\
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"0.001, 0.001, 0.001");
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}
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fall_constraint(CONSTRAINT_TABLE) {
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values("0.001, 0.001, 0.001",\
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"0.001, 0.001, 0.001",\
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"0.001, 0.001, 0.001");
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}
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}
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}
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pin(WEb){
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direction : input;
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capacitance : 0.2091;
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timing(){
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timing_type : setup_rising;
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related_pin : "clk";
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rise_constraint(CONSTRAINT_TABLE) {
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values("0.009, 0.009, 0.009",\
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"0.009, 0.009, 0.009",\
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"0.009, 0.009, 0.009");
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}
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fall_constraint(CONSTRAINT_TABLE) {
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values("0.009, 0.009, 0.009",\
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"0.009, 0.009, 0.009",\
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"0.009, 0.009, 0.009");
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}
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}
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timing(){
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timing_type : hold_rising;
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related_pin : "clk";
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rise_constraint(CONSTRAINT_TABLE) {
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values("0.001, 0.001, 0.001",\
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"0.001, 0.001, 0.001",\
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"0.001, 0.001, 0.001");
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}
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fall_constraint(CONSTRAINT_TABLE) {
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values("0.001, 0.001, 0.001",\
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"0.001, 0.001, 0.001",\
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"0.001, 0.001, 0.001");
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}
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}
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}
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pin(clk){
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clock : true;
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direction : input;
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capacitance : 0.2091;
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timing(){
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timing_type :"min_pulse_width";
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related_pin : clk;
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rise_constraint(scalar) {
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values("0.0");
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}
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fall_constraint(scalar) {
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values("0.0");
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}
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}
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timing(){
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timing_type :"minimum_period";
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related_pin : clk;
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rise_constraint(scalar) {
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values("0.0");
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}
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fall_constraint(scalar) {
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values("0.0");
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}
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}
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}
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}
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}
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