mirror of https://github.com/VLSIDA/OpenRAM.git
Add new DFF. Create DFF module. Start dff_array, not tested.
This commit is contained in:
Matt Guthaus
parent
767990ca3b
commit
0804a1eceb
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@ -0,0 +1,29 @@
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import globals
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import design
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from math import log
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import design
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from tech import GDS,layer
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import utils
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class dff(design.design):
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"""
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Memory address flip-flop
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"""
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pin_names = ["d", "clk", "q", "vdd", "gnd"]
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(width,height) = utils.get_libcell_size("dff", GDS["unit"], layer["boundary"])
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pin_map = utils.get_libcell_pins(pin_names, "dff", GDS["unit"], layer["boundary"])
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def __init__(self, name="dff"):
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design.design.__init__(self, name)
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self.width = dff.width
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self.height = dff.height
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self.pin_map = dff.pin_map
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def analytical_delay(self, slew, load = 0.0):
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# dont know how to calculate this now, use constant in tech file
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from tech import spice
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result = self.return_delay(spice["dff_delay"], spice["dff_slew"])
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return result
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@ -0,0 +1,138 @@
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import debug
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import design
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from tech import drc
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from math import log
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from vector import vector
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from globals import OPTS
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class dff_array(design.design):
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"""
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This is a simple row (or multiple rows) of flops.
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Unlike the data flops, these are never spaced out.
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"""
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def __init__(self, rows, columns, name=""):
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self.rows = rows
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self.columns = columns
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if name=="":
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name = "dff_array_c{0}_w{1}".format(columns,word_size)
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design.design.__init__(self, name)
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debug.info(1, "Creating {}".format(self.name))
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c = reload(__import__(OPTS.dff))
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self.mod_dff = getattr(c, OPTS.dff)
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self.ms = self.mod_dff("dff")
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self.add_mod(self.ms)
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self.width = self.columns * self.ms.width
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self.height = self.rows * self.ms.height
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self.create_layout()
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def create_layout(self):
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self.add_pins()
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self.create_dff_array()
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self.add_layout_pins()
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self.DRC_LVS()
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def add_pins(self):
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for row in range(self.rows):
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for col in range(self.columns):
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self.add_pin("din[{0}][{1}]".format(row,col))
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for row in range(self.rows):
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for col in range(self.columns):
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self.add_pin("dout[{0}][{1}]".format(row,col))
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#self.add_pin("dout_bar[{0}]".format(i))
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self.add_pin("clk")
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self.add_pin("vdd")
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self.add_pin("gnd")
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def create_dff_array(self):
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self.ms_inst={}
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for row in range(self.rows):
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for col in range(self.columns):
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name = "Xdff_r{0}_c{1}".format(row,col)
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if (row % 2 == 0):
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base = vector(i*self.ms.width,0)
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mirror = "R0"
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else:
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base = vector((i+1)*self.ms.width,0)
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mirror = "MY"
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self.ms_inst[row,col]=self.add_inst(name=name,
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mod=self.ms,
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offset=base,
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mirror=mirror)
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self.connect_inst(["din[{0}][{1}]".format(row,col),
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"dout[{0}][{1}]".format(row,col),
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"clk",
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"vdd",
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"gnd"])
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def add_layout_pins(self):
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for i in range(self.word_size):
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for gnd_pin in self.ms_inst[i].get_pins("gnd"):
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if gnd_pin.layer!="metal2":
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continue
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self.add_layout_pin(text="gnd",
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layer="metal2",
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offset=gnd_pin.ll(),
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width=gnd_pin.width(),
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height=gnd_pin.height())
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din_pins = self.ms_inst[i].get_pins("din")
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for din_pin in din_pins:
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self.add_layout_pin(text="din[{}]".format(i),
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layer=din_pin.layer,
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offset=din_pin.ll(),
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width=din_pin.width(),
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height=din_pin.height())
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dout_pin = self.ms_inst[i].get_pin("dout")
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self.add_layout_pin(text="dout[{}]".format(i),
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layer="metal2",
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offset=dout_pin.ll(),
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width=dout_pin.width(),
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height=dout_pin.height())
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doutbar_pin = self.ms_inst[i].get_pin("dout_bar")
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self.add_layout_pin(text="dout_bar[{}]".format(i),
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layer="metal2",
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offset=doutbar_pin.ll(),
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width=doutbar_pin.width(),
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height=doutbar_pin.height())
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# Continous clk rail along with label.
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self.add_layout_pin(text="clk",
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layer="metal1",
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offset=self.ms_inst[0].get_pin("clk").ll().scale(0,1),
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width=self.width,
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height=drc["minwidth_metal1"])
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# Continous vdd rail along with label.
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for vdd_pin in self.ms_inst[i].get_pins("vdd"):
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if vdd_pin.layer!="metal1":
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continue
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self.add_layout_pin(text="vdd",
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layer="metal1",
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offset=vdd_pin.ll().scale(0,1),
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width=self.width,
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height=drc["minwidth_metal1"])
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# Continous gnd rail along with label.
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for gnd_pin in self.ms_inst[i].get_pins("gnd"):
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if gnd_pin.layer!="metal1":
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continue
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self.add_layout_pin(text="gnd",
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layer="metal1",
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offset=gnd_pin.ll().scale(0,1),
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width=self.width,
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height=drc["minwidth_metal1"])
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def analytical_delay(self, slew, load=0.0):
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return self.ms.analytical_delay(slew=slew, load=load)
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@ -58,6 +58,8 @@ class options(optparse.Values):
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decoder = "hierarchical_decoder"
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ms_flop = "ms_flop"
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ms_flop_array = "ms_flop_array"
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dff = "dff"
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dff_array = "dff_array"
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control_logic = "control_logic"
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bitcell_array = "bitcell_array"
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sense_amp = "sense_amp"
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@ -0,0 +1,40 @@
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#!/usr/bin/env python2.7
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"""
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Run a regresion test on a dff_array.
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"""
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import unittest
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from testutils import header,openram_test
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import sys,os
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sys.path.append(os.path.join(sys.path[0],".."))
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import globals
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from globals import OPTS
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import debug
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class dff_array_test(openram_test):
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def runTest(self):
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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global verify
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import verify
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OPTS.check_lvsdrc = False
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import dff_array
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debug.info(2, "Testing dff_array for columns=8, word_size=8")
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a = dff_array.dff_array(columns=8, word_size=8)
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self.local_check(a)
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debug.info(2, "Testing dff_array for columns=16, word_size=8")
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a = dff_array.dff_array(columns=16, word_size=8)
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self.local_check(a)
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OPTS.check_lvsdrc = True
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globals.end_openram()
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# instantiate a copdsay of the class to actually run the test
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if __name__ == "__main__":
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(OPTS, args) = globals.parse_args()
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del sys.argv[1:]
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header(__file__, OPTS.tech_name)
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unittest.main()
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Binary file not shown.
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@ -0,0 +1,46 @@
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* File: DFFPOSX1.pex.netlist
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* Created: Wed Jan 2 18:36:24 2008
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* Program "Calibre xRC"
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* Version "v2007.2_34.24"
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*
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.subckt dff d clk q vdd gnd
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*
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MM21 q a_66_6# gnd gnd NMOS_VTG L=5e-08 W=5e-07
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MM19 a_76_6# a_2_6# a_66_6# gnd NMOS_VTG L=5e-08 W=2.5e-07
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MM20 gnd q a_76_6# gnd NMOS_VTG L=5e-08 W=2.5e-07
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MM18 a_66_6# clk a_61_6# gnd NMOS_VTG L=5e-08 W=2.5e-07
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MM17 a_61_6# a_34_4# gnd gnd NMOS_VTG L=5e-08 W=2.5e-07
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MM10 gnd clk a_2_6# gnd NMOS_VTG L=5e-08 W=5e-07
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MM16 a_34_4# a_22_6# gnd gnd NMOS_VTG L=5e-08 W=2.5e-07
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MM15 gnd a_34_4# a_31_6# gnd NMOS_VTG L=5e-08 W=2.5e-07
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MM14 a_31_6# clk a_22_6# gnd NMOS_VTG L=5e-08 W=2.5e-07
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MM13 a_22_6# a_2_6# a_17_6# gnd NMOS_VTG L=5e-08 W=2.5e-07
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MM12 a_17_6# d gnd gnd NMOS_VTG L=5e-08 W=2.5e-07
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MM11 q a_66_6# vdd vdd PMOS_VTG L=5e-08 W=1e-06
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MM9 vdd q a_76_84# vdd PMOS_VTG L=5e-08 W=2.5e-07
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MM8 a_76_84# clk a_66_6# vdd PMOS_VTG L=5e-08 W=2.5e-07
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MM7 a_66_6# a_2_6# a_61_74# vdd PMOS_VTG L=5e-08 W=5e-07
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MM6 a_61_74# a_34_4# vdd vdd PMOS_VTG L=5e-08 W=5e-07
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MM0 vdd clk a_2_6# vdd PMOS_VTG L=5e-08 W=1e-06
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MM5 a_34_4# a_22_6# vdd vdd PMOS_VTG L=5e-08 W=5e-07
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MM4 vdd a_34_4# a_31_74# vdd PMOS_VTG L=5e-08 W=5e-07
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MM3 a_31_74# a_2_6# a_22_6# vdd PMOS_VTG L=5e-08 W=5e-07
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MM2 a_22_6# clk a_17_74# vdd PMOS_VTG L=5e-08 W=5e-07
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MM1 a_17_74# d vdd vdd PMOS_VTG L=5e-08 W=5e-07
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* c_9 a_66_6# 0 0.271997f
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* c_20 clk 0 0.350944f
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* c_27 q 0 0.202617f
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* c_32 a_76_84# 0 0.0210573f
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* c_38 a_76_6# 0 0.0204911f
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* c_45 a_34_4# 0 0.172306f
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* c_55 a_2_6# 0 0.283119f
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* c_59 a_22_6# 0 0.157312f
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* c_64 d 0 0.0816386f
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* c_73 gnd 0 0.254131f
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* c_81 vdd 0 0.23624f
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*
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*.include "dff.pex.netlist.dff.pxi"
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*
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.ends
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*
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*
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@ -274,6 +274,11 @@ spice["msflop_hold"] = 1 # DFF hold time in ps
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spice["msflop_delay"] = 20.5 # DFF Clk-to-q delay in ps
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spice["msflop_slew"] = 13.1 # DFF output slew in ps w/ no load
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spice["msflop_in_cap"] = 0.2091 # Input capacitance of ms_flop (Din) [Femto-farad]
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spice["dff_setup"] = 9 # DFF setup time in ps
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spice["dff_hold"] = 1 # DFF hold time in ps
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spice["dff_delay"] = 20.5 # DFF Clk-to-q delay in ps
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spice["dff_slew"] = 13.1 # DFF output slew in ps w/ no load
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spice["dff_in_cap"] = 0.2091 # Input capacitance of ms_flop (Din) [Femto-farad]
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###################################################
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Binary file not shown.
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magic
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tech scmos
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timestamp 1090351116
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<< nwell >>
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rect -8 48 104 105
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<< ntransistor >>
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rect 7 6 9 26
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rect 87 6 89 26
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<< ptransistor >>
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rect 7 54 9 94
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rect 15 74 17 94
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rect 21 74 23 94
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<< ndiffusion >>
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rect 2 25 7 26
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rect 89 6 90 25
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<< pdiffusion >>
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rect 2 93 7 94
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rect 6 54 7 93
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<< ndcontact >>
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rect 2 6 6 25
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<< pdcontact >>
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rect 2 54 6 93
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<< psubstratepcontact >>
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rect -2 -2 2 2
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rect 14 -2 18 2
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rect 30 -2 34 2
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<< nsubstratencontact >>
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rect -2 98 2 102
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rect 14 98 18 102
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rect 30 98 34 102
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rect 46 98 50 102
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<< polysilicon >>
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rect 7 94 9 96
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rect 7 4 9 6
|
||||
rect 15 4 17 6
|
||||
rect 20 4 22 6
|
||||
rect 29 4 31 6
|
||||
rect 34 4 36 6
|
||||
rect 43 4 45 6
|
||||
rect 59 4 61 6
|
||||
rect 64 4 66 6
|
||||
rect 74 4 76 6
|
||||
rect 79 4 81 6
|
||||
rect 87 4 89 6
|
||||
<< polycontact >>
|
||||
rect 13 42 17 46
|
||||
rect 6 33 10 37
|
||||
rect 27 50 31 54
|
||||
rect 21 34 25 38
|
||||
rect 35 67 39 71
|
||||
rect 41 57 45 61
|
||||
rect 26 19 30 23
|
||||
rect 35 19 39 23
|
||||
rect 49 67 53 71
|
||||
rect 55 59 59 63
|
||||
rect 70 61 74 65
|
||||
rect 55 33 59 37
|
||||
rect 73 47 77 51
|
||||
rect 81 41 85 45
|
||||
rect 75 27 79 31
|
||||
<< metal1 >>
|
||||
rect -2 102 98 103
|
||||
rect 2 98 14 102
|
||||
rect 18 98 30 102
|
||||
rect 34 98 46 102
|
||||
rect 50 98 62 102
|
||||
rect 66 98 78 102
|
||||
rect 82 98 98 102
|
||||
rect -2 97 98 98
|
||||
rect 10 94 14 97
|
||||
rect 2 93 6 94
|
||||
rect 24 93 28 94
|
||||
rect 18 74 24 77
|
||||
rect 38 93 42 97
|
||||
rect 46 93 50 94
|
||||
rect 54 93 58 97
|
||||
rect 67 93 73 94
|
||||
rect 67 74 68 93
|
||||
rect 72 74 73 93
|
||||
rect 82 93 86 97
|
||||
rect 46 71 49 74
|
||||
rect 39 68 49 71
|
||||
rect 22 57 41 60
|
||||
rect 48 60 55 63
|
||||
rect 48 54 51 60
|
||||
rect 67 56 70 65
|
||||
rect 6 50 27 52
|
||||
rect 31 51 51 54
|
||||
rect 58 53 70 56
|
||||
rect 90 93 94 94
|
||||
rect 2 49 30 50
|
||||
rect 34 46 38 47
|
||||
rect 17 43 38 46
|
||||
rect 10 34 21 37
|
||||
rect 58 37 61 53
|
||||
rect 90 51 94 54
|
||||
rect 77 48 94 51
|
||||
rect 70 41 81 44
|
||||
rect 25 34 55 37
|
||||
rect 10 33 14 34
|
||||
rect 2 25 6 26
|
||||
rect 10 25 14 26
|
||||
rect 27 23 30 34
|
||||
rect 59 34 61 37
|
||||
rect 90 31 94 48
|
||||
rect 79 28 94 31
|
||||
rect 90 25 94 28
|
||||
rect 39 19 49 22
|
||||
rect 46 16 49 19
|
||||
rect 18 15 28 16
|
||||
rect 18 13 24 15
|
||||
rect 37 15 42 16
|
||||
rect 41 6 42 15
|
||||
rect 46 15 50 16
|
||||
rect 54 15 58 16
|
||||
rect 66 15 73 16
|
||||
rect 66 13 68 15
|
||||
rect 67 6 68 13
|
||||
rect 72 6 73 15
|
||||
rect 10 3 14 6
|
||||
rect 37 3 42 6
|
||||
rect 54 3 58 6
|
||||
rect 82 3 86 6
|
||||
rect -2 2 98 3
|
||||
rect 2 -2 14 2
|
||||
rect 18 -2 30 2
|
||||
rect 34 -2 46 2
|
||||
rect 50 -2 62 2
|
||||
rect 66 -2 78 2
|
||||
rect 82 -2 98 2
|
||||
rect -2 -3 98 -2
|
||||
<< m2contact >>
|
||||
rect 18 70 22 74
|
||||
rect 66 70 70 74
|
||||
rect 18 57 22 61
|
||||
rect 2 50 6 54
|
||||
rect 66 40 70 44
|
||||
rect 2 26 6 30
|
||||
rect 18 16 22 20
|
||||
rect 66 16 70 20
|
||||
<< metal2 >>
|
||||
rect 18 61 22 70
|
||||
rect 2 30 6 50
|
||||
rect 18 20 22 57
|
||||
rect 66 44 70 70
|
||||
rect 66 20 70 40
|
||||
<< m1p >>
|
||||
rect 34 43 38 47
|
||||
rect 90 43 94 47
|
||||
rect 10 33 14 37
|
||||
<< labels >>
|
||||
<< end >>
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
* Positive edge-triggered FF
|
||||
.subckt dff d q clk vdd gnd
|
||||
M0 vdd clk a_2_6# vdd p w=12u l=0.6u
|
||||
+ ad=0p pd=0u as=0p ps=0u
|
||||
M1 a_17_74# d vdd vdd p w=6u l=0.6u
|
||||
+ ad=0p pd=0u as=0p ps=0u
|
||||
M2 a_22_6# clk a_17_74# vdd p w=6u l=0.6u
|
||||
+ ad=0p pd=0u as=0p ps=0u
|
||||
M3 a_31_74# a_2_6# a_22_6# vdd p w=6u l=0.6u
|
||||
+ ad=0p pd=0u as=0p ps=0u
|
||||
M4 vdd a_34_4# a_31_74# vdd p w=6u l=0.6u
|
||||
+ ad=0p pd=0u as=0p ps=0u
|
||||
M5 a_34_4# a_22_6# vdd vdd p w=6u l=0.6u
|
||||
+ ad=0p pd=0u as=0p ps=0u
|
||||
M6 a_61_74# a_34_4# vdd vdd p w=6u l=0.6u
|
||||
+ ad=0p pd=0u as=0p ps=0u
|
||||
M7 a_66_6# a_2_6# a_61_74# vdd p w=6u l=0.6u
|
||||
+ ad=0p pd=0u as=0p ps=0u
|
||||
M8 a_76_84# clk a_66_6# vdd p w=3u l=0.6u
|
||||
+ ad=0p pd=0u as=0p ps=0u
|
||||
M9 vdd q a_76_84# vdd p w=3u l=0.6u
|
||||
+ ad=0p pd=0u as=0p ps=0u
|
||||
M10 gnd clk a_2_6# gnd n w=6u l=0.6u
|
||||
+ ad=0p pd=0u as=0p ps=0u
|
||||
M11 q a_66_6# vdd vdd p w=12u l=0.6u
|
||||
+ ad=0p pd=0u as=0p ps=0u
|
||||
M12 a_17_6# d gnd gnd n w=3u l=0.6u
|
||||
+ ad=0p pd=0u as=0p ps=0u
|
||||
M13 a_22_6# a_2_6# a_17_6# gnd n w=3u l=0.6u
|
||||
+ ad=0p pd=0u as=0p ps=0u
|
||||
M14 a_31_6# clk a_22_6# gnd n w=3u l=0.6u
|
||||
+ ad=0p pd=0u as=0p ps=0u
|
||||
M15 gnd a_34_4# a_31_6# gnd n w=3u l=0.6u
|
||||
+ ad=0p pd=0u as=0p ps=0u
|
||||
M16 a_34_4# a_22_6# gnd gnd n w=3u l=0.6u
|
||||
+ ad=0p pd=0u as=0p ps=0u
|
||||
M17 a_61_6# a_34_4# gnd gnd n w=3u l=0.6u
|
||||
+ ad=0p pd=0u as=0p ps=0u
|
||||
M18 a_66_6# clk a_61_6# gnd n w=3u l=0.6u
|
||||
+ ad=0p pd=0u as=0p ps=0u
|
||||
M19 a_76_6# a_2_6# a_66_6# gnd n w=3u l=0.6u
|
||||
+ ad=0p pd=0u as=0p ps=0u
|
||||
M20 gnd q a_76_6# gnd n w=3u l=0.6u
|
||||
+ ad=0p pd=0u as=0p ps=0u
|
||||
M21 q a_66_6# gnd gnd n w=6u l=0.6u
|
||||
+ ad=0p pd=0u as=0p ps=0u
|
||||
.ends dff
|
||||
|
|
@ -238,6 +238,11 @@ spice["msflop_hold"] = 1 # DFF hold time in ps
|
|||
spice["msflop_delay"] = 20.5 # DFF Clk-to-q delay in ps
|
||||
spice["msflop_slew"] = 13.1 # DFF output slew in ps w/ no load
|
||||
spice["msflop_in_cap"] = 9.8242 # Input capacitance of ms_flop (Din) [Femto-farad]
|
||||
spice["dff_setup"] = 9 # DFF setup time in ps
|
||||
spice["dff_hold"] = 1 # DFF hold time in ps
|
||||
spice["dff_delay"] = 20.5 # DFF Clk-to-q delay in ps
|
||||
spice["dff_slew"] = 13.1 # DFF output slew in ps w/ no load
|
||||
spice["dff_in_cap"] = 9.8242 # Input capacitance of ms_flop (Din) [Femto-farad]
|
||||
|
||||
|
||||
###################################################
|
||||
|
|
|
|||
Loading…
Reference in New Issue