Connect dff array clk in rows and columns.

This commit is contained in:
Matt Guthaus 2018-02-14 16:46:26 -08:00
parent 2d87dcda46
commit 9559421ca8
4 changed files with 52 additions and 21 deletions

View File

@ -78,7 +78,7 @@ class dff_array(design.design):
layer="metal1",
offset=vdd_pin.ll(),
width=self.width,
height=drc["minwidth_metal1"])
height=self.m1_width)
# Continous gnd rail along with label.
gnd_pin=self.dff_insts[0,y].get_pin("gnd")
@ -86,12 +86,13 @@ class dff_array(design.design):
layer="metal1",
offset=gnd_pin.ll(),
width=self.width,
height=drc["minwidth_metal1"])
height=self.m1_width)
for y in range(self.rows):
for x in range(self.columns):
din_pin = self.dff_insts[x,y].get_pin("d")
debug.check(din_pin.layer=="metal2","DFF d pin not on metal2")
self.add_layout_pin(text="din[{0}][{1}]".format(x,y),
layer=din_pin.layer,
offset=din_pin.ll(),
@ -99,20 +100,41 @@ class dff_array(design.design):
height=din_pin.height())
dout_pin = self.dff_insts[x,y].get_pin("q")
debug.check(dout_pin.layer=="metal2","DFF q pin not on metal2")
self.add_layout_pin(text="dout[{0}][{1}]".format(x,y),
layer="metal1",
layer=dout_pin.layer,
offset=dout_pin.ll(),
width=dout_pin.width(),
height=dout_pin.height())
# # Continous clk rail along with label.
# self.add_layout_pin(text="clk",
# layer="metal1",
# offset=self.dff_insts[0].get_pin("clk").ll().scale(0,1),
# width=self.width,
# height=drc["minwidth_metal1"])
# Create vertical spines to a single horizontal rail
clk_pin = self.dff_insts[0,0].get_pin("clk")
debug.check(clk_pin.layer=="metal2","DFF clk pin not on metal2")
if self.columns==1:
self.add_layout_pin(text="clk",
layer="metal2",
offset=clk_pin.ll().scale(1,0),
width=self.m2_width,
height=self.height)
else:
self.add_layout_pin(text="clk",
layer="metal3",
offset=clk_pin.ll().scale(0,1),
width=self.width,
height=self.m3_width)
for x in range(self.columns):
clk_pin = self.dff_insts[x,0].get_pin("clk")
# Make a vertical strip for each column
self.add_layout_pin(text="clk",
layer="metal2",
offset=clk_pin.ll().scale(1,0),
width=self.m2_width,
height=self.height)
# Drop a via to the M3 pin
self.add_via_center(layers=("metal2","via2","metal3"),
offset=clk_pin.center())
def analytical_delay(self, slew, load=0.0):

View File

@ -21,10 +21,18 @@ class dff_array_test(openram_test):
import dff_array
debug.info(2, "Testing dff_array for columns=3, word_size=3")
debug.info(2, "Testing dff_array for 3x3")
a = dff_array.dff_array(rows=3, columns=3)
self.local_check(a)
debug.info(2, "Testing dff_array for 1x3")
a = dff_array.dff_array(rows=1, columns=3)
self.local_check(a)
debug.info(2, "Testing dff_array for 3x1")
a = dff_array.dff_array(rows=3, columns=1)
self.local_check(a)
OPTS.check_lvsdrc = True
globals.end_openram()

View File

@ -1,6 +1,6 @@
magic
tech scmos
timestamp 1518652803
timestamp 1518655545
<< nwell >>
rect -8 48 104 105
<< pwell >>
@ -232,20 +232,18 @@ rect 31 51 51 54
rect 58 53 70 56
rect 90 93 94 94
rect 2 49 30 50
rect 34 46 38 47
rect 17 43 38 46
rect 10 34 21 37
rect 17 43 34 46
rect 14 34 21 37
rect 58 37 61 53
rect 90 51 94 54
rect 77 48 94 51
rect 77 48 90 51
rect 70 41 81 44
rect 25 34 55 37
rect 10 33 14 34
rect 2 25 6 26
rect 10 25 14 26
rect 27 23 30 34
rect 59 34 61 37
rect 90 31 94 48
rect 90 31 94 47
rect 79 28 94 31
rect 90 25 94 28
rect 39 19 49 22
@ -277,6 +275,9 @@ rect 18 70 22 74
rect 66 70 70 74
rect 18 57 22 61
rect 2 50 6 54
rect 34 43 38 47
rect 10 33 14 37
rect 90 47 94 51
rect 66 40 70 44
rect 2 26 6 30
rect 18 16 22 20
@ -292,7 +293,7 @@ rect -2 0 98 100
<< labels >>
rlabel metal1 23 100 23 100 5 vdd
rlabel metal1 38 -1 38 -1 1 gnd
rlabel metal1 11 34 11 34 1 clk
rlabel metal1 24 44 24 44 1 d
rlabel metal1 92 37 92 37 1 q
rlabel m2contact 11 34 11 34 1 clk
rlabel m2contact 36 45 36 45 1 d
rlabel m2contact 91 49 91 49 1 q
<< end >>