mirror of https://github.com/VLSIDA/OpenRAM.git
Connect dff array clk in rows and columns.
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@ -78,7 +78,7 @@ class dff_array(design.design):
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layer="metal1",
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offset=vdd_pin.ll(),
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width=self.width,
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height=drc["minwidth_metal1"])
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height=self.m1_width)
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# Continous gnd rail along with label.
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gnd_pin=self.dff_insts[0,y].get_pin("gnd")
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@ -86,12 +86,13 @@ class dff_array(design.design):
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layer="metal1",
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offset=gnd_pin.ll(),
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width=self.width,
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height=drc["minwidth_metal1"])
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height=self.m1_width)
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for y in range(self.rows):
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for x in range(self.columns):
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din_pin = self.dff_insts[x,y].get_pin("d")
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debug.check(din_pin.layer=="metal2","DFF d pin not on metal2")
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self.add_layout_pin(text="din[{0}][{1}]".format(x,y),
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layer=din_pin.layer,
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offset=din_pin.ll(),
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@ -99,20 +100,41 @@ class dff_array(design.design):
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height=din_pin.height())
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dout_pin = self.dff_insts[x,y].get_pin("q")
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debug.check(dout_pin.layer=="metal2","DFF q pin not on metal2")
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self.add_layout_pin(text="dout[{0}][{1}]".format(x,y),
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layer="metal1",
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layer=dout_pin.layer,
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offset=dout_pin.ll(),
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width=dout_pin.width(),
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height=dout_pin.height())
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# # Continous clk rail along with label.
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# self.add_layout_pin(text="clk",
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# layer="metal1",
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# offset=self.dff_insts[0].get_pin("clk").ll().scale(0,1),
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# width=self.width,
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# height=drc["minwidth_metal1"])
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# Create vertical spines to a single horizontal rail
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clk_pin = self.dff_insts[0,0].get_pin("clk")
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debug.check(clk_pin.layer=="metal2","DFF clk pin not on metal2")
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if self.columns==1:
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self.add_layout_pin(text="clk",
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layer="metal2",
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offset=clk_pin.ll().scale(1,0),
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width=self.m2_width,
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height=self.height)
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else:
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self.add_layout_pin(text="clk",
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layer="metal3",
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offset=clk_pin.ll().scale(0,1),
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width=self.width,
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height=self.m3_width)
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for x in range(self.columns):
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clk_pin = self.dff_insts[x,0].get_pin("clk")
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# Make a vertical strip for each column
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self.add_layout_pin(text="clk",
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layer="metal2",
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offset=clk_pin.ll().scale(1,0),
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width=self.m2_width,
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height=self.height)
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# Drop a via to the M3 pin
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self.add_via_center(layers=("metal2","via2","metal3"),
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offset=clk_pin.center())
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def analytical_delay(self, slew, load=0.0):
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@ -21,10 +21,18 @@ class dff_array_test(openram_test):
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import dff_array
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debug.info(2, "Testing dff_array for columns=3, word_size=3")
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debug.info(2, "Testing dff_array for 3x3")
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a = dff_array.dff_array(rows=3, columns=3)
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self.local_check(a)
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debug.info(2, "Testing dff_array for 1x3")
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a = dff_array.dff_array(rows=1, columns=3)
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self.local_check(a)
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debug.info(2, "Testing dff_array for 3x1")
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a = dff_array.dff_array(rows=3, columns=1)
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self.local_check(a)
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OPTS.check_lvsdrc = True
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globals.end_openram()
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Binary file not shown.
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@ -1,6 +1,6 @@
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magic
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tech scmos
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timestamp 1518652803
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timestamp 1518655545
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<< nwell >>
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rect -8 48 104 105
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<< pwell >>
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@ -232,20 +232,18 @@ rect 31 51 51 54
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rect 58 53 70 56
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rect 90 93 94 94
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rect 2 49 30 50
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rect 34 46 38 47
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rect 17 43 38 46
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rect 10 34 21 37
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rect 17 43 34 46
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rect 14 34 21 37
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rect 58 37 61 53
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rect 90 51 94 54
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rect 77 48 94 51
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rect 77 48 90 51
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rect 70 41 81 44
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rect 25 34 55 37
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rect 10 33 14 34
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rect 2 25 6 26
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rect 10 25 14 26
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rect 27 23 30 34
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rect 59 34 61 37
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rect 90 31 94 48
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rect 90 31 94 47
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rect 79 28 94 31
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rect 90 25 94 28
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rect 39 19 49 22
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@ -277,6 +275,9 @@ rect 18 70 22 74
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rect 66 70 70 74
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rect 18 57 22 61
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rect 2 50 6 54
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rect 34 43 38 47
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rect 10 33 14 37
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rect 90 47 94 51
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rect 66 40 70 44
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rect 2 26 6 30
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rect 18 16 22 20
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@ -292,7 +293,7 @@ rect -2 0 98 100
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<< labels >>
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rlabel metal1 23 100 23 100 5 vdd
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rlabel metal1 38 -1 38 -1 1 gnd
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rlabel metal1 11 34 11 34 1 clk
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rlabel metal1 24 44 24 44 1 d
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rlabel metal1 92 37 92 37 1 q
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rlabel m2contact 11 34 11 34 1 clk
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rlabel m2contact 36 45 36 45 1 d
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rlabel m2contact 91 49 91 49 1 q
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<< end >>
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