mirror of https://github.com/VLSIDA/OpenRAM.git
Add input pin rails to hierarchical decoder for easier connections at SRAM level.
This commit is contained in:
Matt Guthaus
parent
5cf62e82cf
commit
e60d157310
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@ -45,7 +45,8 @@ class hierarchical_decoder(design.design):
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self.add_pins()
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self.create_pre_decoder()
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self.create_row_decoder()
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self.create_vertical_rail()
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self.create_input_rail()
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self.create_predecode_rail()
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self.route_vdd_gnd()
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def add_modules(self):
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@ -89,6 +90,7 @@ class hierarchical_decoder(design.design):
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debug.error("Invalid number of inputs for hierarchical decoder",-1)
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def setup_layout_constants(self):
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self.m1_pitch = contact.m1m2.height + max(self.m1_space,self.m2_space)
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self.m2_pitch = contact.m2m3.height + max(self.m2_space,self.m3_space)
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self.predec_groups = [] # This array is a 2D array.
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@ -115,7 +117,77 @@ class hierarchical_decoder(design.design):
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self.calculate_dimensions()
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def create_input_rail(self):
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""" Create input rails for the predecoders """
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# input bus width plus a spacing track
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input_width = (self.num_inputs+1) * self.m2_pitch
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# inputs should be as high as the decoders
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input_height = self.no_of_pre2x4*self.pre2_4.height + self.no_of_pre2x4*self.pre3_8.height
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# Find the left-most predecoder
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min_x = 0
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if self.no_of_pre2x4 > 0:
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min_x = min(min_x, -self.pre2_4.width)
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if self.no_of_pre3x8 > 0:
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min_x = min(min_x, -self.pre3_8.width)
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for i in range(self.num_inputs):
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x_offset = min_x - input_width + i*self.m2_pitch
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pin_offset = vector(x_offset,0)
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self.add_layout_pin(text="A[{0}]".format(i),
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layer="metal2",
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offset=vector(x_offset,0),
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height=input_height)
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self.connect_input_to_predecodes()
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def connect_input_to_predecodes(self):
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""" Connect the vertical input rail to the predecoders """
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for pre_num in range(self.no_of_pre2x4):
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for i in range(2):
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index = pre_num * 2 + i
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input_pin = self.get_pin("A[{}]".format(index))
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in_name = "in[{}]".format(i)
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decoder_pin = self.pre2x4_inst[pre_num].get_pin(in_name)
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# Offset each decoder pin up so they don't conflit
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decoder_offset = decoder_pin.center() + vector(0,i*self.m2_pitch)
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input_offset = input_pin.center().scale(1,0) + decoder_offset.scale(0,1)
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self.connect_input_rail(decoder_offset, input_offset)
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for pre_num in range(self.no_of_pre3x8):
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for i in range(3):
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index = pre_num * 3 + i + self.no_of_pre2x4 * 2
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input_pin = self.get_pin("A[{}]".format(index))
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in_name = "in[{}]".format(i)
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decoder_pin = self.pre3x8_inst[pre_num].get_pin(in_name)
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# Offset each decoder pin up so they don't conflit
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decoder_offset = decoder_pin.center() + vector(0,i*self.m2_pitch)
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input_offset = input_pin.center().scale(1,0) + decoder_offset.scale(0,1)
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self.connect_input_rail(decoder_offset, input_offset)
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def connect_input_rail(self, input_offset, output_offset):
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""" Connect a vertical M2 coordinate to another vertical M2 coordinate to the predecode inputs """
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self.add_via_center(layers=("metal2", "via2", "metal3"),
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offset=input_offset,
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rotate=90)
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self.add_via_center(layers=("metal2", "via2", "metal3"),
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offset=output_offset,
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rotate=90)
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self.add_path(("metal3"), [input_offset, output_offset])
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def add_pins(self):
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""" Add the module pins """
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@ -189,23 +261,6 @@ class hierarchical_decoder(design.design):
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offset=base))
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self.connect_inst(pins)
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self.add_pre2x4_pins(num)
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def add_pre2x4_pins(self,num):
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""" Add the input pins to the 2x4 predecoder """
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for i in range(2):
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pin = self.pre2x4_inst[num].get_pin("in[{}]".format(i))
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pin_offset = pin.ll()
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pin = self.pre2_4.get_pin("in[{}]".format(i))
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self.add_layout_pin(text="A[{0}]".format(i + 2*num ),
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layer="metal2",
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offset=pin_offset,
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width=pin.width(),
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height=pin.height())
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def add_pre3x8(self,num):
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""" Add 3x8 predecoder to the left of the origin and above any 2x4 decoders """
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@ -233,20 +288,6 @@ class hierarchical_decoder(design.design):
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offset=offset))
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self.connect_inst(pins)
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# The 3x8 predecoders will be stacked, so use yoffset
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self.add_pre3x8_pins(num,offset)
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def add_pre3x8_pins(self,num,offset):
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""" Add the input pins to the 3x8 predecoder at the given offset """
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for i in range(3):
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pin = self.pre3x8_inst[num].get_pin("in[{}]".format(i))
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pin_offset = pin.ll()
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self.add_layout_pin(text="A[{0}]".format(i + 3*num + 2*self.no_of_pre2x4),
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layer="metal2",
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offset=pin_offset,
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width=pin.width(),
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height=pin.height())
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@ -372,7 +413,7 @@ class hierarchical_decoder(design.design):
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def create_vertical_rail(self):
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def create_predecode_rail(self):
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""" Creates vertical metal 2 rails to connect predecoder and decoder stages."""
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# This is not needed for inputs <4 since they have no pre/decode stages.
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@ -401,7 +442,7 @@ class hierarchical_decoder(design.design):
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index = pre_num * 4 + i
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out_name = "out[{}]".format(i)
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pin = self.pre2x4_inst[pre_num].get_pin(out_name)
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self.connect_rail_m3(index, pin)
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self.connect_predecode_rail_m3(index, pin)
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for pre_num in range(self.no_of_pre3x8):
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@ -409,7 +450,7 @@ class hierarchical_decoder(design.design):
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index = pre_num * 8 + i + self.no_of_pre2x4 * 4
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out_name = "out[{}]".format(i)
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pin = self.pre3x8_inst[pre_num].get_pin(out_name)
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self.connect_rail_m3(index, pin)
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self.connect_predecode_rail_m3(index, pin)
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@ -425,17 +466,17 @@ class hierarchical_decoder(design.design):
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if (self.num_inputs == 4 or self.num_inputs == 5):
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for index_A in self.predec_groups[0]:
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for index_B in self.predec_groups[1]:
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self.connect_rail(index_A, self.nand_inst[row_index].get_pin("A"))
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self.connect_rail(index_B, self.nand_inst[row_index].get_pin("B"))
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self.connect_predecode_rail(index_A, self.nand_inst[row_index].get_pin("A"))
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self.connect_predecode_rail(index_B, self.nand_inst[row_index].get_pin("B"))
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row_index = row_index + 1
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elif (self.num_inputs > 5):
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for index_A in self.predec_groups[0]:
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for index_B in self.predec_groups[1]:
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for index_C in self.predec_groups[2]:
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self.connect_rail(index_A, self.nand_inst[row_index].get_pin("A"))
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self.connect_rail(index_B, self.nand_inst[row_index].get_pin("B"))
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self.connect_rail(index_C, self.nand_inst[row_index].get_pin("C"))
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self.connect_predecode_rail(index_A, self.nand_inst[row_index].get_pin("A"))
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self.connect_predecode_rail(index_B, self.nand_inst[row_index].get_pin("B"))
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self.connect_predecode_rail(index_C, self.nand_inst[row_index].get_pin("C"))
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row_index = row_index + 1
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def route_vdd_gnd(self):
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@ -471,7 +512,7 @@ class hierarchical_decoder(design.design):
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self.copy_layout_pin(pre, "gnd")
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def connect_rail(self, rail_index, pin):
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def connect_predecode_rail(self, rail_index, pin):
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""" Connect the routing rail to the given metal1 pin """
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rail_pos = vector(self.rail_x_offsets[rail_index],pin.lc().y)
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self.add_path("metal1", [rail_pos, pin.lc()])
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@ -480,7 +521,7 @@ class hierarchical_decoder(design.design):
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rotate=90)
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def connect_rail_m3(self, rail_index, pin):
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def connect_predecode_rail_m3(self, rail_index, pin):
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""" Connect the routing rail to the given metal1 pin """
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mid_point = vector(pin.cx(), pin.cy()+self.inv.height/2)
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rail_pos = vector(self.rail_x_offsets[rail_index],mid_point.y)
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