mirror of https://github.com/VLSIDA/OpenRAM.git
UPdate tests with new delay and slew names and leakage power.
This commit is contained in:
Matt Guthaus
parent
ea772b36d9
commit
fcacd46866
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@ -280,7 +280,7 @@ class delay():
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# add measure statements for power
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t_initial = period
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t_final = 2*period
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self.stim.gen_meas_power(meas_name="LEAKAGE_POWER",
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self.stim.gen_meas_power(meas_name="leakage_power",
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t_initial=t_initial,
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t_final=t_final)
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@ -563,26 +563,29 @@ class delay():
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for m in ["delay_lh", "delay_hl", "slew_lh", "slew_hl", "read0_power",
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"read1_power", "write0_power", "write1_power", "leakage_power"]:
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char_data[m]=[]
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full_array_leakage = []
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trim_array_leakage = []
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full_array_leakage = {}
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trim_array_leakage = {}
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for load in loads:
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# 2a) Find the leakage power of the trimmmed and UNtrimmed arrays.
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(full_leak, trim_leak)=self.run_power_simulation(feasible_period, load)
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full_array_leakage.append(full_leak)
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trim_array_leakage.append(trim_leak)
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for slew in slews:
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full_array_leakage[load]=full_leak
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trim_array_leakage[load]=trim_leak
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char_data["leakage_power"].append(full_array_leakage[load])
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for slew in slews:
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for load in loads:
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# 2c) Find the delay, dynamic power, and leakage power of the trimmed array.
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(success, delay_results) = self.run_delay_simulation(feasible_period, load, slew)
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debug.check(success,"Couldn't run a simulation. slew={0} load={1}\n".format(slew,load))
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for k,v in delay_results.items():
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if "power" in k:
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# Subtract partial array leakage and add full array leakage for the power measures
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char_data[k].append(v - trim_array_leakage[-1] + full_array_leakage[-1])
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char_data["leakage_power"].append(full_array_leakage[-1])
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char_data[k].append(v - trim_array_leakage[load] + full_array_leakage[load])
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else:
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char_data[k].append(v)
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# 3) Finds the minimum period without degrading the delays by X%
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min_period = self.find_min_period(feasible_period, max(loads), max(slews), feasible_delay_lh, feasible_delay_hl)
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debug.check(type(min_period)==float,"Couldn't find minimum period.")
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@ -323,20 +323,16 @@ class lib:
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self.lib.write(" related_pin : \"clk\"; \n")
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self.lib.write(" timing_type : falling_edge; \n")
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self.lib.write(" cell_rise(CELL_TABLE) {\n")
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rounded_values = map(ch.round_time,self.char_results["delayLH"])
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self.write_values(rounded_values,len(self.loads)," ")
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self.write_values(self.char_results["delay_lh"],len(self.loads)," ")
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self.lib.write(" }\n")
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self.lib.write(" cell_fall(CELL_TABLE) {\n")
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rounded_values = map(ch.round_time,self.char_results["delayHL"])
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self.write_values(rounded_values,len(self.loads)," ")
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self.write_values(self.char_results["delay_hl"],len(self.loads)," ")
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self.lib.write(" }\n")
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self.lib.write(" rise_transition(CELL_TABLE) {\n")
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rounded_values = map(ch.round_time,self.char_results["slewLH"])
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self.write_values(rounded_values,len(self.loads)," ")
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self.write_values(self.char_results["slew_lh"],len(self.loads)," ")
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self.lib.write(" }\n")
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self.lib.write(" fall_transition(CELL_TABLE) {\n")
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rounded_values = map(ch.round_time,self.char_results["slewHL"])
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self.write_values(rounded_values,len(self.loads)," ")
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self.write_values(self.char_results["slew_hl"],len(self.loads)," ")
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self.lib.write(" }\n")
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self.lib.write(" }\n")
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self.lib.write(" }\n")
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@ -51,25 +51,25 @@ class timing_sram_test(openram_test):
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data = d.analyze(probe_address, probe_data,slews,loads)
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#print data
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if OPTS.tech_name == "freepdk45":
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golden_data = {'read1_power': 0.032946500000000004,
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'read0_power': 0.0337812,
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'write0_power': 0.026179099999999997,
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'delay1': [0.0573055],
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'delay0': [0.070554],
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golden_data = {'read1_power': [0.032946500000000004],
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'read0_power': [0.0337812],
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'write0_power': [0.026179099999999997],
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'delay_lh': [0.0573055],
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'delay_hl': [0.070554],
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'min_period': 0.205,
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'write1_power': 0.0361529,
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'slew0': [0.0285185],
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'slew1': [0.0190073]}
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'write1_power': [0.0361529],
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'slew_hl': [0.0285185],
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'slew_lh': [0.0190073]}
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elif OPTS.tech_name == "scn3me_subm":
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golden_data = {'read1_power': 9.589,
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'read0_power': 9.7622,
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'write0_power': 6.928400000000001,
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'delay1': [0.6538954],
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'delay0': [0.9019090999999999],
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golden_data = {'read1_power': [9.589],
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'read0_power': [9.7622],
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'write0_power': [6.928400000000001],
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'delay_lh': [0.6538954],
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'delay_hl': [0.9019090999999999],
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'min_period': 2.344,
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'write1_power': 10.2578,
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'slew0': [0.8321625],
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'slew1': [0.5896232]}
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'write1_power': [10.2578],
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'slew_hl': [0.8321625],
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'slew_lh': [0.5896232]}
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else:
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self.assertTrue(False) # other techs fail
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# Check if no too many or too few results
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@ -47,27 +47,29 @@ class timing_sram_test(openram_test):
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loads = [tech.spice["msflop_in_cap"]*4]
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slews = [tech.spice["rise_time"]*2]
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data = d.analyze(probe_address, probe_data,slews,loads)
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#print data
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print data
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if OPTS.tech_name == "freepdk45":
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golden_data = {'read1_power': 0.03308298,
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'read0_power': 0.03866541,
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'write0_power': 0.02695139,
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'delay1': [0.05840294000000001],
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'delay0': [0.40787249999999997],
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'min_period': 0.781,
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'write1_power': 0.037257830000000006,
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'slew0': [0.035826199999999996],
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'slew1': [0.02059459]}
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golden_data = {'leakage_power': [0.0007348262],
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'delay_lh': [0.05799613],
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'read0_power': [0.0384102],
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'read1_power': [0.03279848],
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'write1_power': [0.03693655],
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'write0_power': [0.02717752],
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'slew_hl': [0.03607912],
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'min_period': 0.742,
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'delay_hl': [0.3929995],
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'slew_lh': [0.02160862]}
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elif OPTS.tech_name == "scn3me_subm":
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golden_data = {'read1_power': 11.416549999999999,
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'read0_power': 11.44908,
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'write0_power': 8.250219,
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'delay1': [0.8018421],
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'delay0': [1.085861],
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golden_data = {'leakage_power': [0.00142014],
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'delay_lh': [0.8018421],
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'read0_power': [11.44908],
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'read1_power': [11.416549999999999],
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'write1_power': [11.718020000000001],
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'write0_power': [8.250219],
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'slew_hl': [0.8273725],
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'min_period': 2.734,
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'write1_power': 11.718020000000001,
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'slew0': [0.8273725],
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'slew1': [0.5730144]}
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'delay_hl': [1.085861],
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'slew_lh': [0.5730144]}
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else:
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self.assertTrue(False) # other techs fail
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