mirror of https://github.com/VLSIDA/OpenRAM.git
Line-wrap pinv debug formatting
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@ -96,7 +96,9 @@ class pinv(pgate.pgate):
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nmos_height_available = 0.5 * tx_height_available - 0.5*drc["poly_to_poly"]
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pmos_height_available = 0.5 * tx_height_available - 0.5*drc["poly_to_poly"]
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debug.info(2,"Height avail {0} PMOS height {1} NMOS height {2}".format(tx_height_available, nmos_height_available, pmos_height_available))
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debug.info(2,"Height avail {0:.4f} PMOS {1:.4f} NMOS {2:.4f}".format(tx_height_available,
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nmos_height_available,
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pmos_height_available))
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# Determine the number of mults for each to fit width into available space
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self.nmos_width = self.nmos_size*drc["minwidth_tx"]
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