mirror of https://github.com/VLSIDA/OpenRAM.git
Fixed measure statement stating times. This commit crashes if there are no readwrite ports.
This commit is contained in:
Hunter Nichols
parent
8a0411279e
commit
775fe7b57c
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@ -226,8 +226,8 @@ class delay():
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targ_val=targ_val,
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trig_dir="RISE",
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targ_dir="FALL",
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trig_td=self.cycle_times[self.read0_cycle],
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targ_td=self.cycle_times[self.read0_cycle])
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trig_td=self.cycle_times[self.measure_cycles["read0_{0}".format(port)]],
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targ_td=self.cycle_times[self.measure_cycles["read0_{0}".format(port)]])
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self.stim.gen_meas_delay(meas_name="DELAY_LH_{0}".format(port),
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trig_name=trig_name,
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@ -236,8 +236,8 @@ class delay():
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targ_val=targ_val,
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trig_dir="RISE",
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targ_dir="RISE",
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trig_td=self.cycle_times[self.read1_cycle],
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targ_td=self.cycle_times[self.read1_cycle])
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trig_td=self.cycle_times[self.measure_cycles["read1_{0}".format(port)]],
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targ_td=self.cycle_times[self.measure_cycles["read1_{0}".format(port)]])
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self.stim.gen_meas_delay(meas_name="SLEW_HL_{0}".format(port),
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trig_name=targ_name,
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@ -246,8 +246,8 @@ class delay():
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targ_val=0.1*self.vdd_voltage,
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trig_dir="FALL",
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targ_dir="FALL",
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trig_td=self.cycle_times[self.read0_cycle],
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targ_td=self.cycle_times[self.read0_cycle])
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trig_td=self.cycle_times[self.measure_cycles["read0_{0}".format(port)]],
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targ_td=self.cycle_times[self.measure_cycles["read0_{0}".format(port)]])
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self.stim.gen_meas_delay(meas_name="SLEW_LH_{0}".format(port),
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trig_name=targ_name,
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@ -256,18 +256,18 @@ class delay():
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targ_val=0.9*self.vdd_voltage,
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trig_dir="RISE",
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targ_dir="RISE",
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trig_td=self.cycle_times[self.read1_cycle],
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targ_td=self.cycle_times[self.read1_cycle])
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trig_td=self.cycle_times[self.measure_cycles["read1_{0}".format(port)]],
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targ_td=self.cycle_times[self.measure_cycles["read1_{0}".format(port)]])
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# add measure statements for power
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t_initial = self.cycle_times[self.read0_cycle]
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t_final = self.cycle_times[self.read0_cycle+1]
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t_initial = self.cycle_times[self.measure_cycles["read0_{0}".format(port)]]
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t_final = self.cycle_times[self.measure_cycles["read0_{0}".format(port)]+1]
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self.stim.gen_meas_power(meas_name="READ0_POWER_{0}".format(port),
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t_initial=t_initial,
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t_final=t_final)
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t_initial = self.cycle_times[self.read1_cycle]
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t_final = self.cycle_times[self.read1_cycle+1]
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t_initial = self.cycle_times[self.measure_cycles["read1_{0}".format(port)]]
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t_final = self.cycle_times[self.measure_cycles["read1_{0}".format(port)]+1]
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self.stim.gen_meas_power(meas_name="READ1_POWER_{0}".format(port),
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t_initial=t_initial,
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t_final=t_final)
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@ -277,14 +277,14 @@ class delay():
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Write the measure statements to quantify the power results for a write port.
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"""
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# add measure statements for power
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t_initial = self.cycle_times[self.write0_cycle]
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t_final = self.cycle_times[self.write0_cycle+1]
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t_initial = self.cycle_times[self.measure_cycles["write0_{0}".format(port)]]
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t_final = self.cycle_times[self.measure_cycles["write0_{0}".format(port)]+1]
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self.stim.gen_meas_power(meas_name="WRITE0_POWER_{0}".format(port),
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t_initial=t_initial,
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t_final=t_final)
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t_initial = self.cycle_times[self.write1_cycle]
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t_final = self.cycle_times[self.write1_cycle+1]
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t_initial = self.cycle_times[self.measure_cycles["write1_{0}".format(port)]]
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t_final = self.cycle_times[self.measure_cycles["write1_{0}".format(port)]+1]
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self.stim.gen_meas_power(meas_name="WRITE1_POWER_{0}".format(port),
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t_initial=t_initial,
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t_final=t_final)
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@ -790,23 +790,27 @@ class delay():
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self.add_write("W data 0 address 11..11 to write value",
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self.probe_address,data_zeros,write_port)
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self.write0_cycle=len(self.cycle_times)-1 # Remember for power measure
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self.measure_cycles["write0_{0}".format(write_port)] = len(self.cycle_times)-1
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#self.write0_cycle=len(self.cycle_times)-1 # Remember for power measure
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# This also ensures we will have a H->L transition on the next read
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self.add_read("R data 1 address 00..00 to set DOUT caps",
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inverse_address,data_zeros,read_port)
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self.add_read("R data 0 address 11..11 to check W0 worked",
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self.probe_address,data_zeros,read_port)
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self.read0_cycle=len(self.cycle_times)-1 # Remember for power measure
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self.probe_address,data_zeros,read_port)
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self.measure_cycles["read0_{0}".format(read_port)] = len(self.cycle_times)-1
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#self.read0_cycle=len(self.cycle_times)-1 # Remember for power measure
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self.add_noop_all_ports("Idle cycle (if read takes >1 cycle)",
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inverse_address,data_zeros)
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self.idle_cycle=len(self.cycle_times)-1 # Remember for power measure
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#Does not seem like is is used anywhere commenting out for now.
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#self.idle_cycle=len(self.cycle_times)-1 # Remember for power measure
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self.add_write("W data 1 address 11..11 to write value",
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self.probe_address,data_ones,write_port)
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self.write1_cycle=len(self.cycle_times)-1 # Remember for power measure
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self.measure_cycles["write1_{0}".format(write_port)] = len(self.cycle_times)-1
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#self.write1_cycle=len(self.cycle_times)-1 # Remember for power measure
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self.add_write("W data 0 address 00..00 to clear DIN caps",
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inverse_address,data_zeros,write_port)
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@ -817,8 +821,9 @@ class delay():
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self.add_read("R data 1 address 11..11 to check W1 worked",
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self.probe_address,data_zeros,read_port)
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self.read1_cycle=len(self.cycle_times)-1 # Remember for power measure
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self.measure_cycles["read1_{0}".format(read_port)] = len(self.cycle_times)-1
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#self.read1_cycle=len(self.cycle_times)-1 # Remember for power measure
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self.add_noop_all_ports("Idle cycle (if read takes >1 cycle))",
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self.probe_address,data_zeros)
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@ -833,6 +838,7 @@ class delay():
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# Cycle times (positive edge) with comment
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self.cycle_comments = []
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self.cycle_times = []
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self.measure_cycles = {}
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# Readwrite port Control logic signals each cycle
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self.web_values = {readwrite_port:[] for readwrite_port in self.readwrite_ports}
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@ -853,7 +859,7 @@ class delay():
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#for i in range(self.addr_size):
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# self.addr_values.append([])
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#Temporary logic. Loop through all ports with characterize logic.
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#Temporary logic. Loop through all readwrite ports with characterize logic.
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cur_write_port = None
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for readwrite_port in self.readwrite_ports:
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self.gen_test_cycles_one_port(readwrite_port, readwrite_port)
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@ -864,8 +870,11 @@ class delay():
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write_pos = 0
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read_pos = 0
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while True:
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#Exit when all ports have been characterized
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if write_pos >= len(self.write_ports) and read_pos >= len(self.read_ports):
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break
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#Select new write and/or read ports for the next cycle
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if write_pos < len(self.write_ports):
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cur_write_port = self.write_ports[write_pos]
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write_pos+=1
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@ -452,9 +452,9 @@ class lib:
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self.char_results = self.d.analytical_delay(self.sram,self.slews,self.loads)
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else:
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#Temporary Workaround to here to set # of ports. Crashes if set in config file.
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#OPTS.rw_ports = 2
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#OPTS.rw_ports = 1
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#OPTS.r_ports = 1
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#OPTS.w_ports = 2
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#OPTS.w_ports = 1
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probe_address = "1" * self.sram.addr_size
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probe_data = self.sram.word_size - 1
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