Added new scmos test with a bigger design. Added error checks for not found label and not found pin shapes.

compiler/gdsMill/gdsMill/vlsiLayout.py

@@ -2,6 +2,7 @@ from gdsPrimitives import *
 from datetime import *
 import mpmath
 import gdsPrimitives
+import debug
 
 class VlsiLayout:
     """Class represent a hierarchical layout"""
@@ -252,7 +253,8 @@ class VlsiLayout:
         Method to change the root pointer to another layout.
         """
 
-        if self.debug: print "DEBUG:  GdsMill vlsiLayout: changeRoot: %s "%newRoot
+        if self.debug:
+            debug.info(0,"DEBUG:  GdsMill vlsiLayout: changeRoot: %s "%newRoot)
     
         # Determine if newRoot exists
         #  layoutToAdd (default) or nameOfLayout
@@ -272,7 +274,7 @@ class VlsiLayout:
         """
         offsetInLayoutUnits = (self.userUnits(offsetInMicrons[0]),self.userUnits(offsetInMicrons[1]))
         if self.debug==1: 
-            print "DEBUG:  GdsMill vlsiLayout: addInstance: type %s, nameOfLayout "%type(layoutToAdd),nameOfLayout
+            debug.info(0,"DEBUG:  GdsMill vlsiLayout: addInstance: type %s, nameOfLayout "%type(layoutToAdd),nameOfLayout)
 
 
 
@@ -286,7 +288,8 @@ class VlsiLayout:
             StructureFound = False
             for structure in layoutToAdd.structures:
                 if StructureName in structure: 
-                    if self.debug: print "DEBUG:  Structure %s Found"%StructureName
+                    if self.debug:
+                        debug.info(1,"DEBUG:  Structure %s Found"%StructureName)
                     StructureFound = True
 
 
@@ -581,7 +584,8 @@ class VlsiLayout:
     def getLayoutBorder(self,borderlayer):
         for boundary in self.structures[self.rootStructureName].boundaries:
             if boundary.drawingLayer==borderlayer:
-                if self.debug: print "Find border "+str(boundary.coordinates)
+                if self.debug:
+                    debug.info(1,"Find border "+str(boundary.coordinates))
                 left_bottom=boundary.coordinates[0]
                 right_top=boundary.coordinates[2]
                 cellSize=[right_top[0]-left_bottom[0],right_top[1]-left_bottom[1]]
@@ -658,6 +662,7 @@ class VlsiLayout:
                 label_layer = Text.drawingLayer
                 label_coordinate = Text.coordinates[0]
 
+        debug.check(label_layer!=None,"Did not find label {0}.".format(label_name))
         return (label_coordinate, label_layer)
 
 

compiler/router/router.py

@@ -99,6 +99,8 @@ class router:
             # repack the shape as a pair of vectors rather than four values
             new_pin_shapes.append([vector(pin_shape[0],pin_shape[1]),vector(pin_shape[2],pin_shape[3])])
             
+        debug.check(len(new_pin_shapes)>0,"Did not find any pin shapes for {0}.".format(str(pin)))
+        
         return (pin_layer,new_pin_shapes)
 
     def find_blockages(self):
@@ -295,8 +297,10 @@ class router:
         Mark the grids that are in the pin rectangle ranges to have the source property. 
         """
         (pin_layer,self.source_pin_shapes) = self.find_pin(src)
+
         zindex = 0 if pin_layer==self.horiz_layer_number else 1
         self.source_pin_zindex = zindex
+
         for shape in self.source_pin_shapes:
             shape_in_tracks=self.convert_shape_to_tracks(shape)
             debug.info(1,"Set source: " + str(src) + " " + str(shape_in_tracks) + " z=" + str(zindex))
@@ -308,8 +312,10 @@ class router:
         Mark the grids that are in the pin rectangle ranges to have the target property. 
         """
         (pin_layer,self.target_pin_shapes) = self.find_pin(src)
+
         zindex = 0 if pin_layer==self.horiz_layer_number else 1
         self.target_pin_zindex = zindex
+        
         for shape in self.target_pin_shapes:
             shape_in_tracks=self.convert_shape_to_tracks(shape)  
             debug.info(1,"Set target: " + str(src) + " " + str(shape_in_tracks) + " z=" + str(zindex))

compiler/router/tests/07_big_scmos_test.py

@@ -0,0 +1,86 @@
+#!/usr/bin/env python2.7
+"Run a regresion test the library cells for DRC"
+
+import unittest
+from testutils import header
+import sys,os
+sys.path.append(os.path.join(sys.path[0],"../.."))
+sys.path.append(os.path.join(sys.path[0],".."))
+import globals
+import debug
+import calibre
+
+OPTS = globals.OPTS
+
+class big_scmos_test(unittest.TestCase):
+    """
+    Simplest two pin route test with no blockages using the pin locations instead of labels.
+    """
+
+    def runTest(self):
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
+
+        import design
+        import router
+
+        class gdscell(design.design):
+            """
+            A generic GDS design that we can route on.
+            """
+            def __init__(self, name):
+                #design.design.__init__(self, name)
+                debug.info(2, "Create {0} object".format(name))
+                self.name = name
+                self.gds_file = "{0}/{1}.gds".format(os.path.dirname(os.path.realpath(__file__)),name)
+                self.sp_file = "{0}/{1}.sp".format(os.path.dirname(os.path.realpath(__file__)),name)
+                design.hierarchy_layout.layout.__init__(self, name)
+                design.hierarchy_spice.spice.__init__(self, name)
+            
+        class routing(design.design):
+            """
+            A generic GDS design that we can route on.
+            """
+            def __init__(self, name, gdsname):
+                design.design.__init__(self, name)
+                debug.info(2, "Create {0} object".format(name))
+
+                cell = gdscell(gdsname)
+                self.add_inst(name=gdsname,
+                              mod=cell,
+                              offset=[0,0])
+                self.connect_inst([])
+                
+                self.gdsname = "{0}/{1}.gds".format(os.path.dirname(os.path.realpath(__file__)),gdsname)
+                r=router.router(self.gdsname)
+                layer_stack =("metal3","via2","metal2")
+                # first pin doesn't overlap a rectangle
+                #r.route(layer_stack,src="a_2_7",dest="B")
+                r.route(layer_stack,src="A",dest="B")
+                r.add_route(self)
+
+        if OPTS.tech_name=="scn3me_subm":
+            r = routing("test1", "07_big_scmos_test")
+            self.local_check(r)
+        else:
+            debug.warning("Test must be run in scn3me_subm")
+                
+        # fails if there are any DRC errors on any cells
+        globals.end_openram()
+
+
+    def local_check(self, r):
+        tempgds = OPTS.openram_temp + "temp.gds"
+        r.gds_write(tempgds)
+        self.assertFalse(calibre.run_drc(r.name, tempgds))
+        os.remove(tempgds)
+
+
+                             
+
+
+# instantiate a copy of the class to actually run the test
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main()