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Rename test classes.

This commit is contained in:
mguthaus 2017-04-15 07:49:05 -07:00
parent 2350be8e39
commit 7cac1a0357
5 changed files with 18 additions and 26 deletions
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7
compiler/router/router.py
View File

@ -118,12 +118,17 @@ class router:
for layer in self.layers:
self.write_obstacle(self.top_name)
def clear_pins(self):
def clear(self):
"""
Reset the source and destination pins to start a new routing.
Convert the source/dest to blockages.
Keep the other blockages.
Clear other pins from blockages?
"""
self.source = []
self.dest = []
def route(self, layers, src, dest):
"""

2
compiler/router/tests/02_blockages_test.py
View File

@ -11,7 +11,7 @@ import debug
import calibre
class no_blockages_test(unittest.TestCase):
class blockages_test(unittest.TestCase):
def runTest(self):
globals.init_openram("config_{0}".format(OPTS.tech_name))

2
compiler/router/tests/03_same_layer_pins_test.py
View File

@ -11,7 +11,7 @@ import debug
import calibre
class no_blockages_test(unittest.TestCase):
class same_layer_pins_test(unittest.TestCase):
def runTest(self):
globals.init_openram("config_{0}".format(OPTS.tech_name))

17
compiler/router/tests/04_diff_layer_pins_test.py
View File

@ -11,7 +11,7 @@ import debug
import calibre
class no_blockages_test(unittest.TestCase):
class diff_layer_pins_test(unittest.TestCase):
def runTest(self):
globals.init_openram("config_{0}".format(OPTS.tech_name))
@ -49,21 +49,12 @@ class no_blockages_test(unittest.TestCase):
self.gdsname = "{0}/{1}.gds".format(os.path.dirname(os.path.realpath(__file__)),gdsname)
r=router.router(self.gdsname)
layer_stack =("metal1","via1","metal2")
(src_rect,path,dest_rect)=r.route(layer_stack,src="A",dest="B")
self.add_rect(layer=layer_stack[0],
offset=src_rect[0],
width=src_rect[1].x-src_rect[0].x,
height=src_rect[1].y-src_rect[0].y)
self.add_wire(layer_stack,path)
self.add_rect(layer=layer_stack[0],
offset=dest_rect[0],
width=dest_rect[1].x-dest_rect[0].x,
height=dest_rect[1].y-dest_rect[0].y)
r.route(layer_stack,src="A",dest="B")
r.add_route(self)
r = routing("test1", "AB_diff_layer_pins")
r = routing("test1", "04_diff_layer_pins_test")
self.local_check(r)
# fails if there are any DRC errors on any cells

16
compiler/router/tests/05_two_nets_test.py
View File

@ -11,7 +11,7 @@ import debug
import calibre
class no_blockages_test(unittest.TestCase):
class two_nets_test(unittest.TestCase):
def runTest(self):
globals.init_openram("config_{0}".format(OPTS.tech_name))
@ -49,18 +49,14 @@ class no_blockages_test(unittest.TestCase):
self.gdsname = "{0}/{1}.gds".format(os.path.dirname(os.path.realpath(__file__)),gdsname)
r=router.router(self.gdsname)
layer_stack =("metal1","via1","metal2")
path=r.route(layer_stack,src="A",dest="B")
self.add_wire(layer_stack,path)
r.route(layer_stack,src="A",dest="B")
r.add_route(self)
path=r.route(layer_stack,src="C",dest="D")
self.add_wire(layer_stack,path)
r.rg.view()
r.route(layer_stack,src="A",dest="B")
r.add_route(self)
r = routing("test1", "ABCD_two_nets")
r = routing("test1", "05_two_nets_test")
self.local_check(r)
# fails if there are any DRC errors on any cells