mirror of https://github.com/VLSIDA/OpenRAM.git
Fix width of decoder with new input bus. Bank tests work again.
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019512bc25
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@ -116,8 +116,6 @@ class hierarchical_decoder(design.design):
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def create_input_rail(self):
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""" Create input rails for the predecoders """
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# input bus width plus a spacing track
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input_width = (self.num_inputs+1) * self.m2_pitch
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# inputs should be as high as the decoders
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input_height = self.no_of_pre2x4*self.pre2_4.height + self.no_of_pre3x8*self.pre3_8.height
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@ -129,7 +127,7 @@ class hierarchical_decoder(design.design):
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min_x = min(min_x, -self.pre3_8.width)
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for i in range(self.num_inputs):
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x_offset = min_x - input_width + i*self.m2_pitch
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x_offset = min_x - self.input_routing_width + i*self.m2_pitch
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pin_offset = vector(x_offset,0)
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self.add_layout_pin(text="A[{0}]".format(i),
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layer="metal2",
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@ -220,12 +218,14 @@ class hierarchical_decoder(design.design):
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nand_width = self.nand2.width
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else:
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nand_width = self.nand3.width
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self.routing_width = self.m2_pitch*self.total_number_of_predecoder_outputs
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self.internal_routing_width = self.m2_pitch*self.total_number_of_predecoder_outputs
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self.row_decoder_height = self.inv.height * self.rows
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self.input_routing_width = (self.num_inputs+1) * self.m2_pitch
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# Calculates height and width of hierarchical decoder
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self.height = self.row_decoder_height
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self.width = self.predecoder_width + self.routing_width + nand_width + self.inv.width
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self.width = self.input_routing_width + self.predecoder_width \
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+ self.internal_routing_width + nand_width + self.inv.width
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def create_pre_decoder(self):
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""" Creates pre-decoder and places labels input address [A] """
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@ -347,7 +347,7 @@ class hierarchical_decoder(design.design):
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self.nand_inst.append(self.add_inst(name=name,
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mod=nand_mod,
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offset=[self.routing_width, y_off],
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offset=[self.internal_routing_width, y_off],
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mirror=mirror))
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@ -359,9 +359,9 @@ class hierarchical_decoder(design.design):
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z_pin = self.inv.get_pin("Z")
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if (self.num_inputs == 4 or self.num_inputs == 5):
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x_off = self.routing_width + self.nand2.width
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x_off = self.internal_routing_width + self.nand2.width
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else:
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x_off = self.routing_width + self.nand3.width
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x_off = self.internal_routing_width + self.nand3.width
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self.inv_inst = []
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for row in range(self.rows):
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@ -421,7 +421,7 @@ class hierarchical_decoder(design.design):
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self.rail_x_offsets = []
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for i in range(self.total_number_of_predecoder_outputs):
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# The offsets go into the negative x direction
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# assuming the predecodes are placed at (self.routing_width,0)
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# assuming the predecodes are placed at (self.internal_routing_width,0)
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x_offset = self.m2_pitch * i
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self.rail_x_offsets.append(x_offset+0.5*self.m2_width)
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self.add_rect(layer="metal2",
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