mirror of https://github.com/VLSIDA/OpenRAM.git
Specify file format for sp spice extension.
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@ -44,8 +44,8 @@ EOF
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3. netgen can perform LVS with:
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#!/bin/sh
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netgen -noconsole <<EOF
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readnet $1.spice
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readnet $1.sp
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readnet spice $1.spice
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readnet spice $1.sp
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ignore class c
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equate class {$1.spice nfet} {$2.sp n}
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equate class {$1.spice pfet} {$2.sp p}
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@ -113,8 +113,8 @@ def write_netgen_script(cell_name, sp_name):
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f = open(run_file, "w")
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f.write("#!/bin/sh\n")
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f.write("{} -noconsole << EOF\n".format(OPTS.lvs_exe[1]))
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f.write("readnet {}.spice\n".format(cell_name))
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f.write("readnet {}\n".format(sp_name))
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f.write("readnet spice {}.spice\n".format(cell_name))
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f.write("readnet spice {}\n".format(sp_name))
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f.write("ignore class c\n")
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f.write("permute transistors\n")
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f.write("equate class {{{0}.spice nfet}} {{{1} n}}\n".format(cell_name, sp_name))
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