mirror of https://github.com/VLSIDA/OpenRAM.git
Rotate the output pins of the control logic. Need to fix this permanently.
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@ -624,8 +624,10 @@ class layout(lef.lef):
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# not on the right layer
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if pin.layer != route_layer:
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self.add_via_center(layers=layer_stack,
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offset=pin_pos,
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rotate=90)
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offset=pin_pos)
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# FIXME: output pins tend to not be rotate, but supply pins are. Make consistent?
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# We only need a via if they happened to align perfectly
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# so the add_wire didn't add a via
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