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Revert change. Add gnd pin to right on bitline load.

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This commit is contained in:
Matt Guthaus
2018-07-19 13:26:12 -07:00
parent ea53066966
commit beee8229d1
2 changed files with 5 additions and 16 deletions
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compiler/modules/bitcell_array.py
+2 -3
View File
@@ -80,10 +80,8 @@ class bitcell_array(design.design):
def add_layout_pins(self):
""" Add the layout pins """
row_list = self.cell.list_row_pins()
column_list = self.cell.list_column_pins()
offset = vector(0.0, 0.0)
for col in range(self.column_size):
for cell_column in column_list:
@@ -97,6 +95,7 @@ class bitcell_array(design.design):
# increments to the next column width
offset.x += self.cell.width
row_list = self.cell.list_row_pins()
offset.x = 0.0
for row in range(self.row_size):
for cell_row in row_list:
compiler/modules/replica_bitline.py
+3 -13
View File
@@ -142,7 +142,7 @@ class replica_bitline(design.design):
pin = self.rbl_inst.get_pin(wl)
if pin.layer != "metal1":
continue
self.add_power_pin("gnd", pin.center())
self.add_power_pin("gnd", pin.rc())
def route_supplies(self):
@@ -161,20 +161,10 @@ class replica_bitline(design.design):
pin = self.rbl_inv_inst.get_pin("vdd")
self.add_power_pin("vdd", pin.lc())
# Replica bitcell and the inverter need to be routed up to M3
# Replica bitcell needs to be routed up to M3
for pin_name in ["vdd", "gnd"]:
for pin in self.rbc_inst.get_pins(pin_name):
# Drop to M1 if needed
if pin.layer == "metal1":
self.add_via_center(layers=("metal1", "via1", "metal2"),
offset=pin.center(),
rotate=90)
# Always drop to M2
self.add_via_center(layers=("metal2", "via2", "metal3"),
offset=pin.center())
self.add_layout_pin_rect_center(text=pin_name,
layer="metal3",
offset=pin.center())
self.add_power_pin(pin_name, pin.center())