mirror of https://github.com/VLSIDA/OpenRAM.git
Move bank select logic to a self contained module.
This commit is contained in:
Matt Guthaus
parent
0f721a3d40
commit
98fb1173df
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@ -0,0 +1,238 @@
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import sys
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from tech import drc, parameter
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import debug
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import design
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import contact
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from pinv import pinv
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from pnand2 import pnand2
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from pnor2 import pnor2
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from vector import vector
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from globals import OPTS
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class bank_select(design.design):
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"""Create a bank select signal that is combined with an array of
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NOR+INV gates to gate the control signals in case of multiple
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banks are created in upper level SRAM module
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"""
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def __init__(self, name="bank_select"):
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design.design.__init__(self, name)
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# Number of control lines in the bus
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self.num_control_lines = 6
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# The order of the control signals on the control bus:
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self.input_control_signals = ["clk_buf", "tri_en_bar", "tri_en", "clk_bar", "w_en", "s_en"]
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# These will be outputs of the gaters if this is multibank
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self.control_signals = ["gated_"+str for str in self.input_control_signals]
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for i in range(self.num_control_lines):
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input_name = self.input_control_signals[i]
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self.add_pin(input_name)
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for i in range(self.num_control_lines):
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gated_name = self.control_signals[i]
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self.add_pin(gated_name)
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self.create_modules()
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self.calculate_module_offsets()
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self.add_modules()
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self.route_modules()
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self.DRC_LVS()
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def create_modules(self):
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""" Create modules for later instantiation """
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# 1x Inverter
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self.inv = pinv()
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self.add_mod(self.inv)
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# 4x Inverter
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self.inv4x = pinv(4)
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self.add_mod(self.inv4x)
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self.nor2 = pnor2()
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self.add_mod(self.nor2)
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self.nand2 = pnand2()
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self.add_mod(self.nand2)
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def calculate_module_offsets(self):
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# M1/M2 routing pitch is based on contacted pitch
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self.m1_pitch = contact.m1m2.height + max(self.m1_space,self.m2_space)
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self.m2_pitch = contact.m2m3.height + max(self.m2_space,self.m3_space)
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# left of gnd rail is the "bus start"
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self.xoffset_nand = self.inv4x.width + 2*self.m2_pitch + drc["pwell_to_nwell"]
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self.xoffset_nor = self.inv4x.width + 2*self.m2_pitch + drc["pwell_to_nwell"]
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self.xoffset_inv = max(self.xoffset_nand + self.nand2.width, self.xoffset_nor + self.nor2.width)
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self.xoffset_bank_sel_inv = 0
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self.xoffset_inputs = 0
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# Above the bottom rails (plus a pitch to allow vias)
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self.yoffset_minpoint = self.m1_pitch
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self.yoffset_maxpoint = self.num_control_lines * self.inv.height
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def add_modules(self):
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# bank select inverter
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self.bank_select_inv_position = vector(self.xoffset_bank_sel_inv,
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self.yoffset_minpoint)
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# bank select inverter (must be made unique if more than one OR)
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self.bank_sel_inv=self.add_inst(name="bank_sel_inv",
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mod=self.inv,
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offset=[self.xoffset_bank_sel_inv, self.yoffset_minpoint])
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self.connect_inst(["bank_sel", "bank_sel_bar", "vdd", "gnd"])
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self.logic_inst = []
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self.inv_inst = []
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for i in range(self.num_control_lines):
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input_name = self.input_control_signals[i]
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gated_name = self.control_signals[i]
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name_nand = "nand_{}".format(input_name)
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name_nor = "nor_{}".format(input_name)
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name_inv = "inv_{}".format(input_name)
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y_offset = self.yoffset_minpoint + self.inv.height * i
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if i%2:
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y_offset += self.inv.height
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mirror = "MX"
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else:
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mirror = ""
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# These require OR (nor2+inv) gates since they are active low.
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# (writes occur on clk low)
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if input_name in ("clk_buf", "tri_en_bar"):
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self.logic_inst.append(self.add_inst(name=name_nor,
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mod=self.nor2,
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offset=[self.xoffset_nor, y_offset],
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mirror=mirror))
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self.connect_inst([input_name,
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"bank_sel_bar",
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gated_name+"_temp_bar",
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"vdd",
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"gnd"])
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# the rest are AND (nand2+inv) gates
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else:
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self.logic_inst.append(self.add_inst(name=name_nand,
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mod=self.nand2,
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offset=[self.xoffset_nand, y_offset],
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mirror=mirror))
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bank_sel_signal = "bank_sel"
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self.connect_inst([input_name,
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"bank_sel",
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gated_name+"_temp_bar",
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"vdd",
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"gnd"])
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# They all get inverters on the output
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self.inv_inst.append(self.add_inst(name=name_inv,
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mod=self.inv4x,
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offset=[self.xoffset_inv, y_offset],
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mirror=mirror))
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self.connect_inst([gated_name+"_temp_bar",
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gated_name,
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"vdd",
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"gnd"])
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def route_modules(self):
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# bank_sel is vertical wire
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bank_sel_inv_pin = self.bank_sel_inv.get_pin("A")
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xoffset_bank_sel = bank_sel_inv_pin.lx()
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bank_sel_line_pos = vector(xoffset_bank_sel, self.yoffset_minpoint)
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bank_sel_line_end = vector(xoffset_bank_sel, self.yoffset_maxpoint)
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self.add_path("metal2", [bank_sel_line_pos, bank_sel_line_end])
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self.add_via_center(layers=("metal1","via1","metal2"),
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offset=bank_sel_inv_pin.lc())
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# Route the pin to the left edge as well
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bank_sel_pin_pos=vector(0, self.yoffset_minpoint)
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bank_sel_pin_end=vector(bank_sel_line_pos.x, bank_sel_pin_pos.y)
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self.add_layout_pin_center_segment(text="bank_sel",
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layer="metal3",
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start=bank_sel_pin_pos,
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end=bank_sel_pin_end)
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self.add_via_center(layers=("metal2","via2","metal3"),
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offset=bank_sel_pin_end,
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rotate=90)
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# bank_sel_bar is vertical wire
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bank_sel_bar_pin = self.bank_sel_inv.get_pin("Z")
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xoffset_bank_sel_bar = bank_sel_bar_pin.rx()
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self.add_label_pin(text="bank_sel_bar",
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layer="metal2",
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offset=vector(xoffset_bank_sel_bar, self.yoffset_minpoint),
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height=2*self.inv.height)
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self.add_via_center(layers=("metal1","via1","metal2"),
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offset=bank_sel_bar_pin.rc())
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for i in range(self.num_control_lines):
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logic_inst = self.logic_inst[i]
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inv_inst = self.inv_inst[i]
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input_name = self.input_control_signals[i]
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gated_name = self.control_signals[i]
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if input_name in ("clk_buf", "tri_en_bar"):
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xoffset_bank_signal = xoffset_bank_sel_bar
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else:
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xoffset_bank_signal = xoffset_bank_sel
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# Connect the logic output to inverter input
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pre = logic_inst.get_pin("Z").lc()
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out_position = logic_inst.get_pin("Z").rc() + vector(0.5*self.m1_width,0)
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in_position = inv_inst.get_pin("A").lc() + vector(0.5*self.m1_width,0)
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post = inv_inst.get_pin("A").rc()
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self.add_path("metal1", [pre, out_position, in_position, post])
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# Connect the logic B input to bank_sel/bank_sel_bar
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logic_pos = logic_inst.get_pin("B").lc() - vector(0.5*contact.m1m2.height,0)
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input_pos = vector(xoffset_bank_signal, logic_pos.y)
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self.add_path("metal2",[logic_pos, input_pos])
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=logic_pos,
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rotate=90)
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# Connect the logic A input to the input pin
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logic_pos = logic_inst.get_pin("A").lc()
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input_pos = vector(0,logic_pos.y)
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=logic_pos,
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rotate=90)
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self.add_via_center(layers=("metal2", "via2", "metal3"),
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offset=logic_pos,
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rotate=90)
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self.add_layout_pin_center_segment(text=input_name,
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layer="metal3",
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start=input_pos,
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end=logic_pos)
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# Add output pins
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out_pin = inv_inst.get_pin("Z")
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self.add_layout_pin(text=gated_name,
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layer=out_pin.layer,
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offset=out_pin.ll(),
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width=inv_inst.rx() - out_pin.lx(),
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height=out_pin.height())
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# Add vdd/gnd supply rails
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gnd_pin = inv_inst.get_pin("gnd")
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left_gnd_pos = vector(0, gnd_pin.cy())
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self.add_layout_pin_center_segment(text="gnd",
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layer="metal1",
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start=left_gnd_pos,
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end=gnd_pin.rc())
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vdd_pin = inv_inst.get_pin("vdd")
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left_vdd_pos = vector(0, vdd_pin.cy())
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self.add_layout_pin_center_segment(text="vdd",
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layer="metal1",
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start=left_vdd_pos,
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end=vdd_pin.rc())
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@ -0,0 +1,36 @@
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#!/usr/bin/env python2.7
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"""
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Run a regresion test on various srams
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"""
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import unittest
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from testutils import header,openram_test
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import sys,os
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sys.path.append(os.path.join(sys.path[0],".."))
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import globals
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from globals import OPTS
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import debug
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class bank_select_test(openram_test):
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def runTest(self):
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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global verify
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import verify
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OPTS.check_lvsdrc = False
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import bank_select
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debug.info(1, "No column mux")
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a = bank_select.bank_select()
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self.local_check(a)
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OPTS.check_lvsdrc = True
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globals.end_openram()
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# instantiate a copy of the class to actually run the test
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if __name__ == "__main__":
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(OPTS, args) = globals.parse_args()
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del sys.argv[1:]
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header(__file__, OPTS.tech_name)
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unittest.main()
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