mirror of https://github.com/VLSIDA/OpenRAM.git
Update unit tests.
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@ -104,12 +104,21 @@ class router:
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for layer in self.layers:
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self.write_obstacle(self.top_name)
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def clear_pins(self):
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self.source = []
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self.dest = []
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def route(self,layers,src, dest):
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def route(self, layers, src, dest):
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"""
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Route a single source-destination net and return
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the simplified rectilinear path.
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"""
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self.clear_pins()
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self.set_layers(layers)
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self.create_routing_grid()
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self.set_source(src)
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self.set_target(dest)
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self.find_blockages()
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# returns the path in tracks
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path = self.rg.route()
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@ -49,7 +49,7 @@ class no_blockages_test(unittest.TestCase):
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r=router.router(gdsname+".gds")
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layer_stack =("metal1","via1","metal2")
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path=r.route(layer_stack,src="A",dest="B")
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r.rg.view()
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#r.rg.view()
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self.add_wire(layer_stack,path)
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@ -49,7 +49,7 @@ class no_blockages_test(unittest.TestCase):
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r=router.router(gdsname+".gds")
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layer_stack =("metal1","via1","metal2")
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path=r.route(layer_stack,src="A",dest="B")
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r.rg.view()
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#r.rg.view()
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self.add_wire(layer_stack,path)
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@ -49,7 +49,7 @@ class no_blockages_test(unittest.TestCase):
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r=router.router(gdsname+".gds")
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layer_stack =("metal1","via1","metal2")
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path=r.route(layer_stack,src="A",dest="B")
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r.rg.view()
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#r.rg.view()
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self.add_wire(layer_stack,path)
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@ -49,7 +49,6 @@ class no_blockages_test(unittest.TestCase):
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r=router.router(gdsname+".gds")
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layer_stack =("metal1","via1","metal2")
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path=r.route(layer_stack,src="A",dest="B")
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r.rg.view()
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self.add_wire(layer_stack,path)
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@ -49,13 +49,17 @@ class no_blockages_test(unittest.TestCase):
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r=router.router(gdsname+".gds")
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layer_stack =("metal1","via1","metal2")
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path=r.route(layer_stack,src="A",dest="B")
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self.add_wire(layer_stack,path)
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path=r.route(layer_stack,src="C",dest="D")
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self.add_wire(layer_stack,path)
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r.rg.view()
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self.add_wire(layer_stack,path)
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r = routing("test1", "AB_diff_layer_pins")
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r = routing("test1", "ABCD_two_nets")
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self.local_check(r)
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# fails if there are any DRC errors on any cells
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Binary file not shown.
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@ -0,0 +1,3 @@
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.SUBCKT cell
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.ENDS cell
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