mirror of https://github.com/VLSIDA/OpenRAM.git
Fix syntax error in sram.py
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f5855ee68a
commit
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@ -135,7 +135,7 @@ class sram(design.design):
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""" Add pins for entire SRAM. """
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for i in range(self.word_size):
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self.add_pin("DATA[{0}]".format(i),"INOUT")
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self.add_pin("DIN[{0}]".format(i),"INPUT")
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for i in range(self.addr_size):
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self.add_pin("ADDR[{0}]".format(i),"INPUT")
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@ -144,6 +144,10 @@ class sram(design.design):
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self.control_logic_outputs=self.control_logic.get_outputs()
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self.add_pin_list(self.control_logic_inputs,"INPUT")
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for i in range(self.word_size):
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self.add_pin("DOUT[{0}]".format(i),"OUTPUT")
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self.add_pin("vdd","POWER")
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self.add_pin("gnd","GROUND")
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@ -151,9 +155,7 @@ class sram(design.design):
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""" Layout creation """
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if self.num_banks == 1:
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self.add_single_bank_modules()
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self.add_single_bank_pins()
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self.route_single_bank()
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sram_1bank.sram_1bank.__init__()
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elif self.num_banks == 2:
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self.add_two_bank_modules()
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self.route_two_banks()
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@ -393,7 +395,7 @@ class sram(design.design):
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pitch=self.m2_pitch,
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offset=self.vertical_bus_offset,
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names=self.control_bus_names,
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length=self.vertical_bus_height))
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length=self.vertical_bus_height)
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self.addr_bus_names=["A[{}]".format(i) for i in range(self.addr_size)]
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self.vert_control_bus_positions.update(self.create_vertical_pin_bus(layer="metal2",
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