mirror of https://github.com/VLSIDA/OpenRAM.git
Getting single bank to work reliably. Removed tri_gate from bank
for now. Will add it in multibank arrays only. Not needed for separate DIN and DOUT ports.
This commit is contained in:
Matt Guthaus
parent
834fbac8de
commit
f3ae29fe0b
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@ -39,6 +39,7 @@ class layout(lef.lef):
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shift the origin in the lowest left corner """
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offset = self.find_lowest_coords()
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self.translate_all(offset)
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return offset
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def get_gate_offset(self, x_offset, height, inv_num):
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"""Gets the base offset and y orientation of stacked rows of gates
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@ -66,7 +66,8 @@ class bank(design.design):
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# Can remove the following, but it helps for debug!
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self.add_lvs_correspondence_points()
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self.offset_all_coordinates()
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# Remember the bank center for further placement
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self.bank_center=self.offset_all_coordinates()
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self.DRC_LVS()
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@ -75,7 +76,7 @@ class bank(design.design):
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for i in range(self.word_size):
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self.add_pin("DOUT[{0}]".format(i),"OUT")
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for i in range(self.word_size):
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self.add_pin("DIN[{0}]".format(i),"IN")
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self.add_pin("BANK_DIN[{0}]".format(i),"IN")
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for i in range(self.addr_size):
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self.add_pin("A[{0}]".format(i),"INPUT")
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@ -95,8 +96,9 @@ class bank(design.design):
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self.route_precharge_to_bitcell_array()
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self.route_col_mux_to_bitcell_array()
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self.route_sense_amp_to_col_mux_or_bitcell_array()
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self.route_sense_amp_to_trigate()
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self.route_tri_gate_out()
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#self.route_sense_amp_to_trigate()
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#self.route_tri_gate_out()
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self.route_sense_amp_out()
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self.route_wordline_driver()
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self.route_write_driver()
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self.route_row_decoder()
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@ -119,7 +121,8 @@ class bank(design.design):
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self.add_column_mux_array()
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self.add_sense_amp_array()
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self.add_write_driver_array()
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self.add_tri_gate_array()
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# Not needed for single bank
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#self.add_tri_gate_array()
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# To the left of the bitcell array
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self.add_row_decoder()
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@ -294,14 +297,15 @@ class bank(design.design):
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def add_write_driver_array(self):
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""" Adding Write Driver """
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y_offset = self.sense_amp_array.height + self.column_mux_height + + self.m2_gap + self.write_driver_array.height
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y_offset = self.sense_amp_array.height + self.column_mux_height \
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+ self.m2_gap + self.write_driver_array.height
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self.write_driver_array_inst=self.add_inst(name="write_driver_array",
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mod=self.write_driver_array,
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offset=vector(0,y_offset).scale(-1,-1))
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temp = []
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for i in range(self.word_size):
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temp.append("DIN[{0}]".format(i))
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temp.append("BANK_DIN[{0}]".format(i))
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for i in range(self.word_size):
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if (self.words_per_row == 1):
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temp.append("bl[{0}]".format(i))
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@ -315,7 +319,7 @@ class bank(design.design):
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def add_tri_gate_array(self):
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""" data tri gate to drive the data bus """
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y_offset = self.sense_amp_array.height+self.column_mux_height \
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+ self.write_driver_array.height + self.m2_gap + self.tri_gate_array.height
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+ self.m2_gap + self.tri_gate_array.height
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self.tri_gate_array_inst=self.add_inst(name="tri_gate_array",
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mod=self.tri_gate_array,
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offset=vector(0,y_offset).scale(-1,-1))
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@ -443,7 +447,7 @@ class bank(design.design):
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self.precharge_array_inst,
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self.sense_amp_array_inst,
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self.write_driver_array_inst,
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self.tri_gate_array_inst,
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# self.tri_gate_array_inst,
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self.row_decoder_inst,
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self.wordline_driver_inst]
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# Add these if we use the part...
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@ -492,7 +496,8 @@ class bank(design.design):
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#the column decoder (if there is one) or the tristate output
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#driver.
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# Leave room for the output below the tri gate.
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tri_gate_min_y_offset = self.tri_gate_array_inst.by() - 3*self.m2_pitch
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#tri_gate_min_y_offset = self.tri_gate_array_inst.by() - 3*self.m2_pitch
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write_driver_min_y_offset = self.write_driver_array_inst.by() - 3*self.m2_pitch
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row_decoder_min_y_offset = self.row_decoder_inst.by()
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if self.col_addr_size > 0:
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col_decoder_min_y_offset = self.col_decoder_inst.by()
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@ -502,10 +507,10 @@ class bank(design.design):
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if self.num_banks>1:
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# The control gating logic is below the decoder
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# Min of the control gating logic and tri gate.
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self.min_y_offset = min(col_decoder_min_y_offset - self.bank_select.height, tri_gate_min_y_offset)
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self.min_y_offset = min(col_decoder_min_y_offset - self.bank_select.height, write_driver_min_y_offset)
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else:
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# Just the min of the decoder logic logic and tri gate.
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self.min_y_offset = min(col_decoder_min_y_offset, tri_gate_min_y_offset)
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self.min_y_offset = min(col_decoder_min_y_offset, write_driver_min_y_offset)
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# The max point is always the top of the precharge bitlines
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# Add a vdd and gnd power rail above the array
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@ -620,6 +625,16 @@ class bank(design.design):
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offset=sa_data_out)
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self.add_path("metal3",[sa_data_out,tri_gate_in])
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def route_sense_amp_out(self):
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""" Add pins for the sense amp output """
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for i in range(self.word_size):
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data_pin = self.sense_amp_array_inst.get_pin("data[{}]".format(i))
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self.add_layout_pin_rect_center(text="DOUT[{}]".format(i),
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layer="metal2",
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offset=data_pin.center(),
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height=data_pin.height(),
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width=data_pin.width()),
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def route_tri_gate_out(self):
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""" Metal 3 routing of tri_gate output data """
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for i in range(self.word_size):
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@ -647,7 +662,7 @@ class bank(design.design):
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for i in range(self.word_size):
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data_name = "data[{}]".format(i)
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din_name = "DIN[{}]".format(i)
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din_name = "BANK_DIN[{}]".format(i)
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self.copy_layout_pin(self.write_driver_array_inst, data_name, din_name)
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@ -749,13 +764,13 @@ class bank(design.design):
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layer="metal2",
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offset=br_pin.center())
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# Add the data output names to the sense amp output
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for i in range(self.word_size):
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data_name = "data[{}]".format(i)
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data_pin = self.sense_amp_array_inst.get_pin(data_name)
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self.add_label(text="sa_out[{}]".format(i),
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layer="metal2",
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offset=data_pin.center())
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# # Add the data output names to the sense amp output
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# for i in range(self.word_size):
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# data_name = "data[{}]".format(i)
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# data_pin = self.sense_amp_array_inst.get_pin(data_name)
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# self.add_label(text="sa_out[{}]".format(i),
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# layer="metal2",
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# offset=data_pin.center())
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# Add labels on the decoder
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for i in range(self.word_size):
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@ -775,8 +790,8 @@ class bank(design.design):
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# Connection from the central bus to the main control block crosses
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# pre-decoder and this connection is in metal3
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connection = []
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connection.append((self.prefix+"tri_en_bar", self.tri_gate_array_inst.get_pin("en_bar").lc()))
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connection.append((self.prefix+"tri_en", self.tri_gate_array_inst.get_pin("en").lc()))
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#connection.append((self.prefix+"tri_en_bar", self.tri_gate_array_inst.get_pin("en_bar").lc()))
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#connection.append((self.prefix+"tri_en", self.tri_gate_array_inst.get_pin("en").lc()))
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connection.append((self.prefix+"clk_buf_bar", self.precharge_array_inst.get_pin("en").lc()))
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connection.append((self.prefix+"w_en", self.write_driver_array_inst.get_pin("en").lc()))
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connection.append((self.prefix+"s_en", self.sense_amp_array_inst.get_pin("en").lc()))
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@ -18,7 +18,7 @@ class dff_array(design.design):
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if name=="":
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name = "dff_array_{0}x{1}".format(rows, columns)
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design.design.__init__(self, name)
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debug.info(1, "Creating {}".format(self.name))
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debug.info(1, "Creating {0} rows={1} cols={2}".format(self.name, self.rows, self.columns))
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from importlib import reload
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c = reload(__import__(OPTS.dff))
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@ -38,33 +38,33 @@ class dff_array(design.design):
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self.DRC_LVS()
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def add_pins(self):
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for y in range(self.rows):
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for x in range(self.columns):
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self.add_pin(self.get_din_name(y,x))
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for y in range(self.rows):
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for x in range(self.columns):
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self.add_pin(self.get_dout_name(y,x))
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for row in range(self.rows):
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for col in range(self.columns):
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self.add_pin(self.get_din_name(row,col))
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for row in range(self.rows):
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for col in range(self.columns):
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self.add_pin(self.get_dout_name(row,col))
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self.add_pin("clk")
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self.add_pin("vdd")
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self.add_pin("gnd")
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def create_dff_array(self):
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self.dff_insts={}
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for y in range(self.rows):
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for x in range(self.columns):
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name = "Xdff_r{0}_c{1}".format(y,x)
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if (y % 2 == 0):
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base = vector(x*self.dff.width,y*self.dff.height)
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for row in range(self.rows):
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for col in range(self.columns):
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name = "Xdff_r{0}_c{1}".format(row,col)
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if (row % 2 == 0):
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base = vector(col*self.dff.width,row*self.dff.height)
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mirror = "R0"
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else:
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base = vector(x*self.dff.width,(y+1)*self.dff.height)
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base = vector(col*self.dff.width,(row+1)*self.dff.height)
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mirror = "MX"
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self.dff_insts[x,y]=self.add_inst(name=name,
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self.dff_insts[row,col]=self.add_inst(name=name,
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mod=self.dff,
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offset=base,
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mirror=mirror)
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self.connect_inst([self.get_din_name(y,x),
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self.get_dout_name(y,x),
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self.connect_inst([self.get_din_name(row,col),
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self.get_dout_name(row,col),
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"clk",
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"vdd",
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"gnd"])
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@ -91,10 +91,9 @@ class dff_array(design.design):
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def add_layout_pins(self):
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for y in range(self.rows):
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for row in range(self.rows):
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# Continous vdd rail along with label.
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vdd_pin=self.dff_insts[0,y].get_pin("vdd")
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vdd_pin=self.dff_insts[row,0].get_pin("vdd")
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self.add_layout_pin(text="vdd",
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layer="metal1",
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offset=vdd_pin.ll(),
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@ -102,7 +101,7 @@ class dff_array(design.design):
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height=self.m1_width)
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# Continous gnd rail along with label.
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gnd_pin=self.dff_insts[0,y].get_pin("gnd")
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gnd_pin=self.dff_insts[row,0].get_pin("gnd")
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self.add_layout_pin(text="gnd",
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layer="metal1",
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offset=gnd_pin.ll(),
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@ -110,19 +109,19 @@ class dff_array(design.design):
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height=self.m1_width)
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for y in range(self.rows):
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for x in range(self.columns):
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din_pin = self.dff_insts[x,y].get_pin("D")
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for row in range(self.rows):
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for col in range(self.columns):
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din_pin = self.dff_insts[row,col].get_pin("D")
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debug.check(din_pin.layer=="metal2","DFF D pin not on metal2")
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self.add_layout_pin(text=self.get_din_name(y,x),
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self.add_layout_pin(text=self.get_din_name(row,col),
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layer=din_pin.layer,
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offset=din_pin.ll(),
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width=din_pin.width(),
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height=din_pin.height())
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dout_pin = self.dff_insts[x,y].get_pin("Q")
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dout_pin = self.dff_insts[row,col].get_pin("Q")
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debug.check(dout_pin.layer=="metal2","DFF Q pin not on metal2")
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self.add_layout_pin(text=self.get_dout_name(y,x),
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self.add_layout_pin(text=self.get_dout_name(row,col),
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layer=dout_pin.layer,
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offset=dout_pin.ll(),
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width=dout_pin.width(),
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@ -145,8 +144,8 @@ class dff_array(design.design):
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offset=vector(0,0),
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width=self.width,
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height=self.m3_width)
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for x in range(self.columns):
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clk_pin = self.dff_insts[x,0].get_pin("clk")
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for col in range(self.columns):
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clk_pin = self.dff_insts[0,col].get_pin("clk")
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# Make a vertical strip for each column
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self.add_layout_pin(text="clk",
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layer="metal2",
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@ -23,6 +23,8 @@ class sram():
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num_words))
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start_time = datetime.datetime.now()
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self.name = name
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if num_banks == 1:
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from sram_1bank import sram_1bank
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self.s=sram_1bank(word_size, num_words, name)
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@ -53,8 +55,6 @@ class sram():
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if not OPTS.is_unit_test:
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print_time("SRAM creation", datetime.datetime.now(), start_time)
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def get_name(self):
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return self.s.name
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def sp_write(self,name):
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self.s.sp_write(name)
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@ -37,14 +37,18 @@ class sram_1bank(sram_base):
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self.add_control_logic(position=control_pos)
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# Leave room for the control routes to the left of the flops
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addr_pos = vector(self.control_logic_inst.lx() + 4*self.m2_pitch,
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row_addr_pos = vector(self.control_logic_inst.lx() + 4*self.m2_pitch,
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control_pos.y + self.control_logic.height + self.m1_pitch)
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self.add_addr_dff(addr_pos)
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self.add_row_addr_dff(row_addr_pos)
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# Leave room for the control routes to the left of the flops
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data_pos = vector(self.control_logic_inst.lx() + 4*self.m2_pitch,
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control_pos.y + self.control_logic.height + self.m1_pitch)
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self.add_addr_dff(addr_pos)
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# Add the column address below the bank under the control
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if self.col_addr_dff:
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col_addr_pos = vector(-self.col_addr_dff.width, -1.5*self.col_addr_dff.height)
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self.add_col_addr_dff(col_addr_pos)
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# Add the data flops below the bank
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data_pos = vector(-self.bank_inst.mod.bank_center.x, -1.5*self.data_dff.height)
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self.add_data_dff(data_pos)
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# two supply rails are already included in the bank, so just 2 here.
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self.width = self.bank.width + self.control_logic.width + 2*self.supply_rail_pitch
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@ -54,15 +58,22 @@ class sram_1bank(sram_base):
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"""
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Add the top-level pins for a single bank SRAM with control.
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"""
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# Connect the control pins as inputs
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for n in self.control_logic_inputs + ["clk"]:
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self.copy_layout_pin(self.control_logic_inst, n)
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for i in range(self.word_size):
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self.copy_layout_pin(self.bank_inst, "DOUT[{}]".format(i))
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for i in range(self.addr_size):
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self.copy_layout_pin(self.addr_dff_inst, "din[{}]".format(i),"ADDR[{}]".format(i))
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# Lower address bits
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for i in range(self.col_addr_size):
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self.copy_layout_pin(self.col_addr_dff_inst, "din[{}]".format(i),"ADDR[{}]".format(i))
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# Upper address bits
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for i in range(self.row_addr_size):
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self.copy_layout_pin(self.row_addr_dff_inst, "din[{}]".format(i),"ADDR[{}]".format(i+self.col_addr_size))
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for i in range(self.word_size):
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self.copy_layout_pin(self.addr_dff_inst, "din[{}]".format(i),"ADDR[{}]".format(i))
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self.copy_layout_pin(self.data_dff_inst, "din[{}]".format(i),"DIN[{}]".format(i))
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def route(self):
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""" Route a single bank SRAM """
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@ -79,14 +90,28 @@ class sram_1bank(sram_base):
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rotate=90)
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# Connect the output of the flops to the bank pins
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for i in range(self.addr_size):
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# Connect the output of the row flops to the bank pins
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for i in range(self.row_addr_size):
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flop_name = "dout[{}]".format(i)
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bank_name = "A[{}]".format(i)
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flop_pin = self.addr_dff_inst.get_pin(flop_name)
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bank_name = "A[{}]".format(i+self.col_addr_size)
|
||||
flop_pin = self.row_addr_dff_inst.get_pin(flop_name)
|
||||
bank_pin = self.bank_inst.get_pin(bank_name)
|
||||
flop_pos = flop_pin.center()
|
||||
bank_pos = vector(bank_pin.cx(),flop_pos.y)
|
||||
bank_pos = bank_pin.center()
|
||||
mid_pos = vector(bank_pos.x,flop_pos.y)
|
||||
self.add_wire(("metal3","via2","metal2"),[flop_pos, mid_pos,bank_pos])
|
||||
self.add_via_center(layers=("metal2","via2","metal3"),
|
||||
offset=flop_pos,
|
||||
rotate=90)
|
||||
|
||||
# Connect the output of the row flops to the bank pins
|
||||
for i in range(self.col_addr_size):
|
||||
flop_name = "dout[{}]".format(i)
|
||||
bank_name = "A[{}]".format(i)
|
||||
flop_pin = self.col_addr_dff_inst.get_pin(flop_name)
|
||||
bank_pin = self.bank_inst.get_pin(bank_name)
|
||||
flop_pos = flop_pin.center()
|
||||
bank_pos = bank_pin.center()
|
||||
self.add_path("metal3",[flop_pos, bank_pos])
|
||||
self.add_via_center(layers=("metal2","via2","metal3"),
|
||||
offset=flop_pos,
|
||||
|
|
@ -95,17 +120,28 @@ class sram_1bank(sram_base):
|
|||
offset=bank_pos,
|
||||
rotate=90)
|
||||
|
||||
# Connect the control pins as inputs
|
||||
for n in self.control_logic_inputs + ["clk"]:
|
||||
self.copy_layout_pin(self.control_logic_inst, n)
|
||||
# Connect the output of the row flops to the bank pins
|
||||
for i in range(self.word_size):
|
||||
flop_name = "dout[{}]".format(i)
|
||||
bank_name = "BANK_DIN[{}]".format(i)
|
||||
flop_pin = self.data_dff_inst.get_pin(flop_name)
|
||||
bank_pin = self.bank_inst.get_pin(bank_name)
|
||||
flop_pos = flop_pin.center()
|
||||
bank_pos = bank_pin.center()
|
||||
mid_pos = vector(bank_pos.x,flop_pos.y)
|
||||
self.add_wire(("metal3","via2","metal2"),[flop_pos, mid_pos,bank_pos])
|
||||
self.add_via_center(layers=("metal2","via2","metal3"),
|
||||
offset=flop_pos,
|
||||
rotate=90)
|
||||
|
||||
|
||||
# Connect the clock between the flops and control module
|
||||
flop_pin = self.addr_dff_inst.get_pin("clk")
|
||||
ctrl_pin = self.control_logic_inst.get_pin("clk_buf")
|
||||
flop_pos = flop_pin.uc()
|
||||
ctrl_pos = ctrl_pin.bc()
|
||||
mid_ypos = 0.5*(ctrl_pos.y+flop_pos.y)
|
||||
mid1_pos = vector(flop_pos.x, mid_ypos)
|
||||
mid2_pos = vector(ctrl_pos.x, mid_ypos)
|
||||
self.add_wire(("metal1","via1","metal2"),[flop_pin.uc(), mid1_pos, mid2_pos, ctrl_pin.bc()])
|
||||
# # Connect the clock between the flops and control module
|
||||
# flop_pin = self.addr_dff_inst.get_pin("clk")
|
||||
# ctrl_pin = self.control_logic_inst.get_pin("clk_buf")
|
||||
# flop_pos = flop_pin.uc()
|
||||
# ctrl_pos = ctrl_pin.bc()
|
||||
# mid_ypos = 0.5*(ctrl_pos.y+flop_pos.y)
|
||||
# mid1_pos = vector(flop_pos.x, mid_ypos)
|
||||
# mid2_pos = vector(ctrl_pos.x, mid_ypos)
|
||||
# self.add_wire(("metal1","via1","metal2"),[flop_pin.uc(), mid1_pos, mid2_pos, ctrl_pin.bc()])
|
||||
|
||||
|
|
|
|||
|
|
@ -32,9 +32,6 @@ class sram_base(design):
|
|||
self.num_words = num_words
|
||||
self.num_banks = num_banks
|
||||
|
||||
def whoami():
|
||||
print("abstract")
|
||||
|
||||
def compute_sizes(self):
|
||||
""" Computes the organization of the memory using bitcell size by trying to make it square."""
|
||||
|
||||
|
|
@ -258,10 +255,18 @@ class sram_base(design):
|
|||
self.add_mod(self.control_logic)
|
||||
|
||||
# Create the address and control flops (but not the clk)
|
||||
dff_size = self.addr_size
|
||||
from dff_array import dff_array
|
||||
self.addr_dff = dff_array(name="dff_array", rows=dff_size, columns=1)
|
||||
self.add_mod(self.addr_dff)
|
||||
self.row_addr_dff = dff_array(name="row_addr_dff", rows=self.row_addr_size, columns=1)
|
||||
self.add_mod(self.row_addr_dff)
|
||||
|
||||
if self.col_addr_size > 0:
|
||||
self.col_addr_dff = dff_array(name="col_addr_dff", rows=1, columns=self.col_addr_size)
|
||||
self.add_mod(self.col_addr_dff)
|
||||
else:
|
||||
self.col_addr_dff = None
|
||||
|
||||
self.data_dff = dff_array(name="data_dff", rows=1, columns=self.word_size)
|
||||
self.add_mod(self.data_dff)
|
||||
|
||||
# Create the bank module (up to four are instantiated)
|
||||
from bank import bank
|
||||
|
|
@ -329,21 +334,49 @@ class sram_base(design):
|
|||
return bank_inst
|
||||
|
||||
|
||||
|
||||
def add_addr_dff(self, position):
|
||||
""" Add and place address and control flops """
|
||||
self.addr_dff_inst = self.add_inst(name="address",
|
||||
mod=self.addr_dff,
|
||||
offset=position)
|
||||
def add_row_addr_dff(self, position):
|
||||
""" Add and place all address flops for the main decoder """
|
||||
self.row_addr_dff_inst = self.add_inst(name="row_address",
|
||||
mod=self.row_addr_dff,
|
||||
offset=position)
|
||||
# inputs, outputs/output/bar
|
||||
inputs = []
|
||||
outputs = []
|
||||
for i in range(self.addr_size):
|
||||
for i in range(self.row_addr_size):
|
||||
inputs.append("ADDR[{}]".format(i+self.col_addr_size))
|
||||
outputs.append("A[{}]".format(i+self.col_addr_size))
|
||||
|
||||
self.connect_inst(inputs + outputs + ["clk_buf", "vdd", "gnd"])
|
||||
|
||||
|
||||
def add_col_addr_dff(self, position):
|
||||
""" Add and place all address flops for the column decoder """
|
||||
self.col_addr_dff_inst = self.add_inst(name="row_address",
|
||||
mod=self.col_addr_dff,
|
||||
offset=position)
|
||||
# inputs, outputs/output/bar
|
||||
inputs = []
|
||||
outputs = []
|
||||
for i in range(self.col_addr_size):
|
||||
inputs.append("ADDR[{}]".format(i))
|
||||
outputs.append("A[{}]".format(i))
|
||||
|
||||
self.connect_inst(inputs + outputs + ["clk_buf", "vdd", "gnd"])
|
||||
|
||||
|
||||
def add_data_dff(self, position):
|
||||
""" Add and place all data flops """
|
||||
self.data_dff_inst = self.add_inst(name="data_dff",
|
||||
mod=self.data_dff,
|
||||
offset=position)
|
||||
# inputs, outputs/output/bar
|
||||
inputs = []
|
||||
outputs = []
|
||||
for i in range(self.word_size):
|
||||
inputs.append("DIN[{}]".format(i))
|
||||
outputs.append("BANK_DIN[{}]".format(i))
|
||||
|
||||
self.connect_inst(inputs + outputs + ["clk_buf_bar", "vdd", "gnd"])
|
||||
|
||||
def add_control_logic(self, position):
|
||||
""" Add and place control logic """
|
||||
inputs = []
|
||||
|
|
|
|||
|
|
@ -32,14 +32,14 @@ class openram_test(unittest.TestCase):
|
|||
a.gds_write(tempgds)
|
||||
|
||||
import verify
|
||||
result=verify.run_drc(a.get_name(), tempgds)
|
||||
result=verify.run_drc(a.name, tempgds)
|
||||
if result != 0:
|
||||
self.fail("DRC failed: {}".format(a.get_name()))
|
||||
self.fail("DRC failed: {}".format(a.name))
|
||||
|
||||
|
||||
result=verify.run_lvs(a.get_name(), tempgds, tempspice, final_verification)
|
||||
result=verify.run_lvs(a.name, tempgds, tempspice, final_verification)
|
||||
if result != 0:
|
||||
self.fail("LVS mismatch: {}".format(a.get_name()))
|
||||
self.fail("LVS mismatch: {}".format(a.name))
|
||||
|
||||
if OPTS.purge_temp:
|
||||
self.cleanup()
|
||||
|
|
|
|||
Loading…
Reference in New Issue