mirror of https://github.com/VLSIDA/OpenRAM.git
Fix unit test to have fanout.
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@ -22,15 +22,16 @@ class replica_bitline_test(openram_test):
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import replica_bitline
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stages=4
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fanout=4
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rows=13
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debug.info(2, "Testing RBL with {0} FO4 stages, {1} rows".format(stages,rows))
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a = replica_bitline.replica_bitline(stages,rows)
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a = replica_bitline.replica_bitline(stages,fanout,rows)
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self.local_check(a)
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stages=8
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rows=100
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debug.info(2, "Testing RBL with {0} FO4 stages, {1} rows".format(stages,rows))
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a = replica_bitline.replica_bitline(stages,rows)
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a = replica_bitline.replica_bitline(stages,fanout,rows)
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self.local_check(a)
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OPTS.check_lvsdrc = True
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