mirror of https://github.com/VLSIDA/OpenRAM.git
Rework hierarchical decoder to not be folded. Remove address from central bank bus and access via side pins now. Eight way column mux now works.
This commit is contained in:
Matt Guthaus
parent
1f81b24e96
commit
bab92fcf38
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@ -30,6 +30,8 @@ class design(hierarchy_spice.spice, hierarchy_layout.layout):
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# These modules ensure unique names or have no changes if they
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# aren't unique
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ok_list = ['ms_flop.ms_flop',
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'dff.dff',
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'dff_buf.dff_buf',
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'bitcell.bitcell',
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'contact.contact',
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'ptx.ptx',
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@ -91,6 +91,8 @@ class spice(verilog.verilog):
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group of modules are generated."""
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if (check and (len(self.insts[-1].mod.pins) != len(args))):
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debug.error("Connections: {}".format(self.insts[-1].mod.pins))
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debug.error("Connections: {}".format(args))
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debug.error("Number of net connections ({0}) does not match last instance ({1})".format(len(self.insts[-1].mod.pins),
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len(args)), 1)
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self.conns.append(args)
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@ -161,17 +161,15 @@ class bank(design.design):
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# The central bus is the column address (one hot) and row address (binary)
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if self.col_addr_size>0:
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self.num_col_addr_lines = 2**self.col_addr_size
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self.num_addr_lines = self.num_col_addr_lines + self.row_addr_size
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else:
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self.num_col_addr_lines = 0
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self.num_addr_lines = self.row_addr_size
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# M1/M2 routing pitch is based on contacted pitch
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self.m1_pitch = contact.m1m2.height + max(self.m1_space,self.m2_space)
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self.m2_pitch = contact.m2m3.height + max(self.m2_space,self.m3_space)
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# The width of this bus is needed to place other modules (e.g. decoder)
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self.central_bus_width = self.m2_pitch * (self.num_control_lines + self.num_addr_lines + 1)
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self.central_bus_width = self.m2_pitch * self.num_control_lines
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@ -362,12 +360,10 @@ class bank(design.design):
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# The predecoder is below the x-axis and the main decoder is above the x-axis
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# The address flop and decoder are aligned in the x coord.
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decoder_x_offset = self.row_decoder.width + self.central_bus_width
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offset = vector(decoder_x_offset,
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self.row_decoder.predecoder_height)
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x_offset = -(self.row_decoder.width + self.central_bus_width + self.wordline_driver.width)
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self.row_decoder_inst=self.add_inst(name="row_decoder",
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mod=self.row_decoder,
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offset=offset.scale(-1,-1))
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offset=vector(x_offset,0))
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temp = []
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for i in range(self.row_addr_size):
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@ -381,12 +377,10 @@ class bank(design.design):
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""" Wordline Driver """
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# The wordline driver is placed to the right of the main decoder width.
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# This means that it slightly overlaps with the hierarchical decoder,
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# but it shares power rails. This may differ for other decoders later...
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x_offset = self.row_decoder.width + self.central_bus_width - self.row_decoder.row_decoder_width
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x_offset = -(self.central_bus_width + self.wordline_driver.width) + self.m2_pitch
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self.wordline_driver_inst=self.add_inst(name="wordline_driver",
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mod=self.wordline_driver,
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offset=vector(x_offset,0).scale(-1,-1))
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offset=vector(x_offset,0))
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temp = []
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for i in range(self.num_rows):
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@ -404,8 +398,8 @@ class bank(design.design):
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Create a 2:4 or 3:8 column address decoder.
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"""
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# Place the col decoder aligned left to row decoder
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x_off = -(self.central_bus_width + self.row_decoder.width)
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y_off = -(self.row_decoder.predecoder_height + self.col_decoder.height + 2*drc["well_to_well"])
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x_off = -(self.row_decoder.width + self.central_bus_width + self.wordline_driver.width)
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y_off = -(self.col_decoder.height + 2*drc["well_to_well"])
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self.col_decoder_inst=self.add_inst(name="col_address_decoder",
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mod=self.col_decoder,
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offset=vector(x_off,y_off))
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@ -445,10 +439,10 @@ class bank(design.design):
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if not self.num_banks > 1:
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return
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xoffset = -(self.central_bus_width + self.bank_select.width)
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x_off = -(self.row_decoder.width + self.central_bus_width + self.wordline_driver.width)
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# extra space to allow vias
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yoffset = self.min_point + 2*self.supply_rail_pitch + self.m1_space
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self.bank_select_pos = vector(xoffset,yoffset)
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y_off = self.min_point + 2*self.supply_rail_pitch + self.m1_space
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self.bank_select_pos = vector(x_off,y_off)
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self.bank_select_inst = self.add_inst(name="bank_select",
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mod=self.bank_select,
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offset=self.bank_select_pos)
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@ -536,12 +530,11 @@ class bank(design.design):
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""" Create the address, supply, and control signal central bus lines. """
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# Overall central bus width. It includes all the column mux lines,
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# control lines, and address flop to decoder lines.
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# and control lines.
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# The bank is at (0,0), so this is to the left of the y-axis.
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# 2 pitches on the right for vias/jogs to access the inputs
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control_bus_x_offset = -self.m2_pitch * (self.num_control_lines)
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address_bus_x_offset = control_bus_x_offset - self.m2_pitch*(self.num_addr_lines)
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control_bus_x_offset = -self.m2_pitch * self.num_control_lines
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# Track the bus offsets for other modules to access
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self.bus_xoffset = {}
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@ -556,35 +549,6 @@ class bank(design.design):
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width=self.m2_width,
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height=self.height)
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# Row address lines (to left of col address lines)
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# goes from bottom of bitcell array down to the bottom of the column decoder/addresses
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for i in range(self.row_addr_size):
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addr_idx = i + self.col_addr_size
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x_offset = address_bus_x_offset + i*self.m2_pitch
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name = "A[{}]".format(addr_idx)
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# Make the xoffset map the center of the rail
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self.bus_xoffset[name]=x_offset + 0.5*self.m2_width
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# Add a label pin for LVS correspondence and visual help inspecting the rail.
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self.add_layout_pin(text=name,
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layer="metal2",
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offset=vector(x_offset, self.min_point),
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width=self.m2_width,
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height=-self.min_point)
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# Column mux lines if there is column mux
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# goes from bottom of bitcell array down to the bottom of the column decoder/addresses
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if self.col_addr_size>0:
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for i in range(self.num_col_addr_lines):
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x_offset = address_bus_x_offset + (i+self.row_addr_size)*self.m2_pitch
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name = "sel[{}]".format(i) # One hot select signals
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# Make the xoffset map the center of the rail
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self.bus_xoffset[name]=x_offset + 0.5*self.m2_width
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# Add a label pin for LVS correspondence
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self.add_label_pin(text=name,
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layer="metal2",
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offset=vector(x_offset, self.col_decoder_inst.by()),
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width=self.m2_width,
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height=-self.col_decoder_inst.by())
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def route_precharge_to_bitcell_array(self):
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@ -654,33 +618,14 @@ class bank(design.design):
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def route_row_decoder(self):
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""" Routes the row decoder inputs and supplies """
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for i in range(self.row_addr_size):
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addr_idx = i + self.col_addr_size
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# before this index, we are using 2x4 decoders
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switchover_index = 2*self.row_decoder.no_of_pre2x4
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# so decide what modulus to perform the height spacing
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if i < switchover_index:
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position_heights = i % 2
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else:
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position_heights = (i-switchover_index) % 3
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# Connect the address rails to the decoder
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# Note that the decoder inputs are long vertical rails so spread out the connections vertically.
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decoder_in_position = self.row_decoder_inst.get_pin("A[{}]".format(i)).lr() \
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+ vector(0,position_heights*self.bitcell.height+self.m2_pitch)
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rail_position = vector(self.bus_xoffset["A[{}]".format(addr_idx)],
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decoder_in_position.y)
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self.add_path("metal1",[decoder_in_position,rail_position])
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decoder_in_via = decoder_in_position - vector(0,0.5*self.m2_width)
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self.add_via(layers=("metal1", "via1", "metal2"),
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offset=decoder_in_via,
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rotate=90)
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# # Create inputs for the row address lines
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# for i in range(self.row_addr_size):
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# addr_idx = i + self.col_addr_size
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# decoder_name = "A[{}]".format(i)
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# addr_name = "A[{}]".format(addr_idx)
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# self.copy_layout_pin(self.row_decoder_inst, decoder_name, addr_name)
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=rail_position,
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rotate=90)
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# Route the power and ground, but only BELOW the y=0 since the
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# others are connected with the wordline driver.
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# These must be on M3 to not interfere with column mux address pins.
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@ -730,70 +675,51 @@ class bank(design.design):
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def route_column_address_lines(self):
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""" Connecting the select lines of column mux to the address bus """
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if not self.col_addr_size>0:
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return
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# Connect the select lines to the column mux
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# These must be in metal3 so that they don't overlap any gnd lines from decoders
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for i in range(self.num_col_addr_lines):
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name = "sel[{}]".format(i)
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mux_addr_pos = self.col_mux_array_inst.get_pin(name).lc()
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wire_pos = vector(self.bus_xoffset[name], mux_addr_pos.y)
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self.add_path("metal1", [wire_pos,mux_addr_pos])
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=wire_pos,
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rotate=90)
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if self.col_addr_size == 1:
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decode_out_pos = self.col_decoder_inst.get_pin("Zb").rc()
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selx_pos = vector(self.bus_xoffset["sel[0]"],decode_out_pos.y)
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self.add_path("metal1",[decode_out_pos, selx_pos])
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=selx_pos,
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rotate=90)
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decode_out_pos = self.col_decoder_inst.get_pin("Z").rc()
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selx_pos = vector(self.bus_xoffset["sel[1]"],decode_out_pos.y)
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self.add_path("metal1",[decode_out_pos, selx_pos])
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=selx_pos,
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rotate=90)
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# Connect to sel[0] and sel[1]
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decode_names = ["Zb", "Z"]
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# The Address LSB
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decode_in_pin = self.col_decoder_inst.get_pin("A")
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pin_pos = vector(decode_in_pin.cx(), self.min_point)
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self.add_layout_pin_center_segment(text="A[0]",
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layer="metal2",
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start=pin_pos,
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end=decode_in_pin.bc())
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self.copy_layout_pin(self.col_decoder_inst, "A", "A[0]")
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elif self.col_addr_size > 1:
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# Route the col decoder outputs to the col select bus
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decode_names = []
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for i in range(self.num_col_addr_lines):
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name = "sel[{}]".format(i)
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decode_out_pos = self.col_decoder_inst.get_pin("out[{}]".format(i)).rc()
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selx_pos = vector(self.bus_xoffset[name],decode_out_pos.y)
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self.add_path("metal1",[decode_out_pos, selx_pos])
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=selx_pos,
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rotate=90)
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decode_names.append("out[{}]".format(i))
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# Route from the col decoder up to the address bus
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for i in range(self.col_addr_size):
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decoder_name = "in[{}]".format(i)
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addr_name = "A[{}]".format(i)
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decode_in_pin = self.col_decoder_inst.get_pin(decoder_name)
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pin_pos = vector(decode_in_pin.cx(), self.min_point)
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self.add_layout_pin_center_segment(text=addr_name,
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layer="metal2",
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start=pin_pos,
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end=decode_in_pin.bc())
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self.copy_layout_pin(self.col_decoder_inst, decoder_name, addr_name)
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# This will do a quick "river route" on two layers.
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# When above the top select line it will offset "inward" again to prevent conflicts.
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# This could be done on a single layer, but we follow preferred direction rules for later routing.
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top_y_offset = self.col_mux_array_inst.get_pin("sel[{}]".format(self.num_col_addr_lines-1)).cy()
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for (decode_name,i) in zip(decode_names,range(self.num_col_addr_lines)):
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mux_name = "sel[{}]".format(i)
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mux_addr_pos = self.col_mux_array_inst.get_pin(mux_name).lc()
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decode_out_pos = self.col_decoder_inst.get_pin(decode_name).center()
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# To get to the edge of the decoder and one track out
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delta_offset = self.col_decoder_inst.rx() - decode_out_pos.x + self.m2_pitch
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if decode_out_pos.y > top_y_offset:
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mid1_pos = vector(decode_out_pos.x + delta_offset + i*self.m2_pitch,decode_out_pos.y)
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else:
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mid1_pos = vector(decode_out_pos.x + delta_offset + (self.num_col_addr_lines-i)*self.m2_pitch,decode_out_pos.y)
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mid2_pos = vector(mid1_pos.x,mux_addr_pos.y)
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self.add_wire(("metal1","via1","metal2"),[decode_out_pos, mid1_pos, mid2_pos, mux_addr_pos])
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# route the gnd rails, add contact to rail as well
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for gnd_pin in self.col_decoder_inst.get_pins("gnd"):
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left_rail_pos = vector(self.left_gnd_x_center, gnd_pin.cy())
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@ -154,12 +154,11 @@ class hierarchical_decoder(design.design):
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else:
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nand_width = self.nand3.width
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self.routing_width = self.metal2_pitch*self.total_number_of_predecoder_outputs
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self.row_decoder_width = nand_width + self.routing_width + self.inv.width
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self.row_decoder_height = self.inv.height * self.rows
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# Calculates height and width of hierarchical decoder
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self.height = self.row_decoder_height
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self.width = self.predecoder_width + self.row_decoder_width
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self.width = self.predecoder_width + self.routing_width + nand_width + self.inv.width
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def create_pre_decoder(self):
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""" Creates pre-decoder and places labels input address [A] """
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@ -479,7 +478,7 @@ class hierarchical_decoder(design.design):
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def connect_rail_m3(self, rail_index, pin):
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""" Connect the routing rail to the given metal1 pin """
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mid_point = vector(pin.cx(), pin.cy()-self.inv.height/2)
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mid_point = vector(pin.cx(), pin.cy()+self.inv.height/2)
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rail_pos = vector(self.rail_x_offsets[rail_index],mid_point.y)
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=pin.center(),
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@ -119,7 +119,7 @@ class single_level_column_mux_array(design.design):
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def add_horizontal_input_rail(self):
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""" Create address input rails on M1 below the mux transistors """
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for j in range(self.words_per_row):
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offset = vector(0, self.route_height - (j+1)*self.m1_pitch)
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offset = vector(0, self.route_height + (j-self.words_per_row)*self.m1_pitch)
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self.add_layout_pin(text="sel[{}]".format(j),
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layer="metal1",
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offset=offset,
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@ -22,6 +22,7 @@ class wordline_driver(design.design):
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self.rows = rows
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self.add_pins()
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self.design_layout()
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self.offset_all_coordinates()
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self.DRC_LVS()
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def add_pins(self):
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@ -28,7 +28,7 @@ class pinvbuf(design.design):
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self.inv2 = pinv(size=inv2_size)
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self.add_mod(self.inv2)
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self.width = self.inv1.width + self.inv2.width
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self.width = 2*self.inv1.width + self.inv2.width
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self.height = 2*self.inv1.height
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self.create_layout()
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120
compiler/sram.py
120
compiler/sram.py
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@ -20,9 +20,15 @@ class sram(design.design):
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c = reload(__import__(OPTS.control_logic))
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self.mod_control_logic = getattr(c, OPTS.control_logic)
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c = reload(__import__(OPTS.dff_array))
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self.mod_dff_array = getattr(c, OPTS.dff_array)
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if num_banks>1:
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# Use a buffered array for big arrays
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# Also ensures we have Qbar when FF doesn't
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c = reload(__import__(OPTS.dff_buf_array))
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self.mod_dff_array = getattr(c, OPTS.dff_buf_array)
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else:
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c = reload(__import__(OPTS.dff_array))
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self.mod_dff_array = getattr(c, OPTS.dff_array)
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c = reload(__import__(OPTS.bitcell))
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self.mod_bitcell = getattr(c, OPTS.bitcell)
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@ -200,6 +206,32 @@ class sram(design.design):
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self.width = self.bank_inst[1].ur().x
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self.height = self.control_logic_inst.uy()
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def add_single_bank_modules(self):
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"""
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This adds the moduels for a single bank SRAM with control
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logic.
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"""
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# No orientation or offset
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self.bank_inst = self.add_bank(0, [0, 0], 1, 1)
|
||||
|
||||
# 3/5/18 MRG: Cannot reference positions inside submodules because boundaries
|
||||
# are not recomputed using instance placement. So, place the control logic such that it aligns
|
||||
# with the top of the SRAM.
|
||||
control_gap = 2*self.m3_width
|
||||
control_pos = vector(-self.control_logic.width-control_gap,
|
||||
self.bank.height-self.control_logic.height-3*self.supply_rail_width)
|
||||
self.add_control_logic(position=control_pos)
|
||||
|
||||
# Leave room for the control routes to the left of the flops
|
||||
addr_pos = vector(self.control_logic_inst.lx() + 4*self.m2_pitch,
|
||||
3*self.supply_rail_pitch)
|
||||
self.add_control_addr_dff(addr_pos)
|
||||
|
||||
self.width = self.bank.width + self.control_logic.height + control_gap
|
||||
self.height = self.bank.height
|
||||
|
||||
|
||||
def route_shared_banks(self):
|
||||
""" Route the shared signals for two and four bank configurations. """
|
||||
|
|
@ -777,9 +809,10 @@ class sram(design.design):
|
|||
|
||||
def create_multi_bank_modules(self):
|
||||
""" Create the multibank address flops and bank decoder """
|
||||
self.msb_address = self.mod_ms_flop_array(name="msb_address",
|
||||
columns=self.num_banks/2,
|
||||
word_size=self.num_banks/2)
|
||||
|
||||
self.msb_address = self.mod_dff_array(name="msb_address",
|
||||
rows=1,
|
||||
columns=self.num_banks/2)
|
||||
self.add_mod(self.msb_address)
|
||||
|
||||
if self.num_banks>2:
|
||||
|
|
@ -794,9 +827,9 @@ class sram(design.design):
|
|||
self.add_mod(self.control_logic)
|
||||
|
||||
# Create the address and control flops (but not the clk)
|
||||
dff_size = self.addr_size + len(self.control_logic.get_inputs())-1
|
||||
self.addr_ctrl_dff = self.mod_dff_array(name="dff_array", rows=dff_size, columns=1)
|
||||
self.add_mod(self.addr_ctrl_dff)
|
||||
dff_size = self.addr_size
|
||||
self.addr_dff = self.mod_dff_array(name="dff_array", rows=dff_size, columns=1)
|
||||
self.add_mod(self.addr_dff)
|
||||
|
||||
# Create the bank module (up to four are instantiated)
|
||||
self.bank = bank(word_size=self.word_size,
|
||||
|
|
@ -902,9 +935,9 @@ class sram(design.design):
|
|||
|
||||
def add_control_addr_dff(self, position):
|
||||
""" Add and place address and control flops """
|
||||
self.addr_ctrl_dff_inst = self.add_inst(name="address",
|
||||
mod=self.addr_ctrl_dff,
|
||||
offset=position)
|
||||
self.addr_dff_inst = self.add_inst(name="address",
|
||||
mod=self.addr_dff,
|
||||
offset=position)
|
||||
# inputs, outputs/output/bar
|
||||
inputs = []
|
||||
outputs = []
|
||||
|
|
@ -912,12 +945,6 @@ class sram(design.design):
|
|||
inputs.append("ADDR[{}]".format(i))
|
||||
outputs.append("A[{}]".format(i))
|
||||
|
||||
for i in self.control_logic_inputs:
|
||||
if i == "clk":
|
||||
continue
|
||||
inputs.append(i)
|
||||
outputs.append(i+"_s")
|
||||
|
||||
self.connect_inst(inputs + outputs + ["clk", "vdd", "gnd"])
|
||||
|
||||
def add_control_logic(self, position):
|
||||
|
|
@ -951,31 +978,6 @@ class sram(design.design):
|
|||
layer="metal2",
|
||||
offset=self.vert_control_bus_positions[n])
|
||||
|
||||
def add_single_bank_modules(self):
|
||||
"""
|
||||
This adds the moduels for a single bank SRAM with control
|
||||
logic.
|
||||
"""
|
||||
|
||||
# No orientation or offset
|
||||
self.bank_inst = self.add_bank(0, [0, 0], 1, 1)
|
||||
|
||||
# 3/5/18 MRG: Cannot reference positions inside submodules because boundaries
|
||||
# are not recomputed using instance placement. So, place the control logic such that it aligns
|
||||
# with the top of the SRAM.
|
||||
control_gap = 2*self.m3_width
|
||||
control_pos = vector(-self.control_logic.width-control_gap,
|
||||
self.bank.height-self.control_logic.height-3*self.supply_rail_width)
|
||||
self.add_control_logic(position=control_pos)
|
||||
|
||||
# Leave room for the control routes to the left of the flops
|
||||
addr_pos = vector(self.control_logic_inst.lx() + 4*self.m2_pitch,
|
||||
3*self.supply_rail_pitch)
|
||||
self.add_control_addr_dff(addr_pos)
|
||||
|
||||
self.width = self.bank.width + self.control_logic.height + control_gap
|
||||
self.height = self.bank.height
|
||||
|
||||
def add_single_bank_pins(self):
|
||||
"""
|
||||
Add the top-level pins for a single bank SRAM with control.
|
||||
|
|
@ -985,13 +987,9 @@ class sram(design.design):
|
|||
self.copy_layout_pin(self.bank_inst, "DATA[{}]".format(i))
|
||||
|
||||
for i in range(self.addr_size):
|
||||
self.copy_layout_pin(self.addr_ctrl_dff_inst, "din[{}]".format(i),"ADDR[{}]".format(i))
|
||||
self.copy_layout_pin(self.addr_dff_inst, "din[{}]".format(i),"ADDR[{}]".format(i))
|
||||
|
||||
ctrl_flops = ["din[{}]".format(i) for i in range(self.addr_size,self.addr_size+3)]
|
||||
for (old,new) in zip(ctrl_flops,["CSb","WEb","OEb"]):
|
||||
self.copy_layout_pin(self.addr_ctrl_dff_inst, old, new)
|
||||
|
||||
self.copy_layout_pin(self.addr_ctrl_dff_inst, "clk")
|
||||
self.copy_layout_pin(self.addr_dff_inst, "clk")
|
||||
|
||||
# Power ring contains the power pins
|
||||
|
||||
|
|
@ -1068,7 +1066,7 @@ class sram(design.design):
|
|||
for i in range(self.addr_size):
|
||||
flop_name = "dout[{}]".format(i)
|
||||
bank_name = "A[{}]".format(i)
|
||||
flop_pin = self.addr_ctrl_dff_inst.get_pin(flop_name)
|
||||
flop_pin = self.addr_dff_inst.get_pin(flop_name)
|
||||
bank_pin = self.bank_inst.get_pin(bank_name)
|
||||
flop_pos = flop_pin.center()
|
||||
bank_pos = vector(bank_pin.cx(),flop_pos.y)
|
||||
|
|
@ -1080,24 +1078,14 @@ class sram(design.design):
|
|||
offset=bank_pos,
|
||||
rotate=90)
|
||||
|
||||
# Connect the output of the flops to the control pins
|
||||
for i in range(3):
|
||||
flop_name = "dout[{}]".format(self.addr_size+i)
|
||||
ctrl_name = ["csb","web","oeb"][i]
|
||||
flop_pin = self.addr_ctrl_dff_inst.get_pin(flop_name)
|
||||
ctrl_pin = self.control_logic_inst.get_pin(ctrl_name)
|
||||
flop_pos = flop_pin.center()
|
||||
ctrl_pos = ctrl_pin.bc()
|
||||
mid_pos = vector(ctrl_pos.x, flop_pos.y)
|
||||
self.add_wire(("metal3","via2","metal2"),[flop_pos, mid_pos, ctrl_pos])
|
||||
self.add_via_center(layers=("metal2","via2","metal3"),
|
||||
offset=flop_pos,
|
||||
rotate=90)
|
||||
# Connect the control pins as inputs
|
||||
for n in self.control_logic_inputs + ["clk"]:
|
||||
self.copy_layout_pin(self.control_logic_inst, n.lower(), n)
|
||||
|
||||
# Connect the clock between the flops and control module
|
||||
# FIXME: Buffered clock should drive the flops, but then
|
||||
# it would change the setup time...
|
||||
flop_pin = self.addr_ctrl_dff_inst.get_pin("clk")
|
||||
flop_pin = self.addr_dff_inst.get_pin("clk")
|
||||
ctrl_pin = self.control_logic_inst.get_pin("clk")
|
||||
flop_pos = flop_pin.uc()
|
||||
ctrl_pos = ctrl_pin.bc()
|
||||
|
|
@ -1111,7 +1099,7 @@ class sram(design.design):
|
|||
""" Route vdd for the control and dff array """
|
||||
|
||||
# Route the vdd rails to the LEFT
|
||||
modules = [ self.control_logic_inst, self.addr_ctrl_dff_inst]
|
||||
modules = [ self.control_logic_inst, self.addr_dff_inst]
|
||||
for inst in modules:
|
||||
for vdd_pin in inst.get_pins("vdd"):
|
||||
if vdd_pin.layer != "metal1":
|
||||
|
|
@ -1140,7 +1128,7 @@ class sram(design.design):
|
|||
""" Route gnd for the control and dff array """
|
||||
|
||||
# Route the gnd rails to the LEFT
|
||||
modules = [ self.control_logic_inst, self.addr_ctrl_dff_inst]
|
||||
modules = [ self.control_logic_inst, self.addr_dff_inst]
|
||||
for inst in modules:
|
||||
for gnd_pin in inst.get_pins("gnd"):
|
||||
if gnd_pin.layer != "metal1":
|
||||
|
|
|
|||
|
|
@ -33,10 +33,9 @@ class multi_bank_test(openram_test):
|
|||
a = bank.bank(word_size=4, num_words=64, words_per_row=4, num_banks=2, name="bank3")
|
||||
self.local_check(a)
|
||||
|
||||
# Eight way has a short circuit of one column mux select to gnd rail
|
||||
# debug.info(1, "Eight way column mux")
|
||||
# a = bank.bank(word_size=2, num_words=128, words_per_row=8, num_banks=2, name="bank4")
|
||||
# self.local_check(a)
|
||||
debug.info(1, "Eight way column mux")
|
||||
a = bank.bank(word_size=2, num_words=128, words_per_row=8, num_banks=2, name="bank4")
|
||||
self.local_check(a)
|
||||
|
||||
OPTS.check_lvsdrc = True
|
||||
globals.end_openram()
|
||||
|
|
|
|||
Loading…
Reference in New Issue