mirror of https://github.com/VLSIDA/OpenRAM.git
Fix unintended unmerge of changes. Bad bad.
This commit is contained in:
Matt Guthaus
parent
a44346110b
commit
4e414b6c15
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@ -204,7 +204,7 @@ class delay():
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trig_val = targ_val = 0.5 * self.vdd_voltage
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# Delay the target to measure after the negative edge
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self.stim.gen_meas_delay(meas_name="DELAY0",
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self.stim.gen_meas_delay(meas_name="DELAY_HL",
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trig_name=trig_name,
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targ_name=targ_name,
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trig_val=trig_val,
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@ -214,7 +214,7 @@ class delay():
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trig_td=self.cycle_times[self.read0_cycle],
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targ_td=self.cycle_times[self.read0_cycle]+0.5*period)
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self.stim.gen_meas_delay(meas_name="DELAY1",
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self.stim.gen_meas_delay(meas_name="DELAY_LH",
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trig_name=trig_name,
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targ_name=targ_name,
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trig_val=trig_val,
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@ -224,7 +224,7 @@ class delay():
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trig_td=self.cycle_times[self.read1_cycle],
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targ_td=self.cycle_times[self.read1_cycle]+0.5*period)
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self.stim.gen_meas_delay(meas_name="SLEW0",
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self.stim.gen_meas_delay(meas_name="SLEW_HL",
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trig_name=targ_name,
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targ_name=targ_name,
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trig_val=0.9*self.vdd_voltage,
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@ -234,7 +234,7 @@ class delay():
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trig_td=self.cycle_times[self.read0_cycle],
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targ_td=self.cycle_times[self.read0_cycle]+0.5*period)
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self.stim.gen_meas_delay(meas_name="SLEW1",
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self.stim.gen_meas_delay(meas_name="SLEW_LH",
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trig_name=targ_name,
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targ_name=targ_name,
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trig_val=0.1*self.vdd_voltage,
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@ -303,20 +303,20 @@ class delay():
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debug.error("Timed out, could not find a feasible period.",2)
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(success, results)=self.run_delay_simulation(feasible_period,load,slew)
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feasible_delay1 = results["delay1"]
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feasible_slew1 = results["slew1"]
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feasible_delay0 = results["delay0"]
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feasible_slew0 = results["slew0"]
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feasible_delay_lh = results["delay_lh"]
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feasible_slew_lh = results["slew_lh"]
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feasible_delay_hl = results["delay_hl"]
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feasible_slew_hl = results["slew_hl"]
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if not success:
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feasible_period = 2 * feasible_period
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continue
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debug.info(1, "Found feasible_period: {0}ns feasible_delay1/0 {1}ns/{2}ns slew {3}ns/{4}ns".format(feasible_period,
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feasible_delay1,
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feasible_delay0,
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feasible_slew1,
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feasible_slew0))
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return (feasible_period, feasible_delay1, feasible_delay0)
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debug.info(1, "Found feasible_period: {0}ns feasible_delay_lh/0 {1}ns/{2}ns slew {3}ns/{4}ns".format(feasible_period,
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feasible_delay_lh,
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feasible_delay_hl,
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feasible_slew_lh,
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feasible_slew_hl))
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return (feasible_period, feasible_delay_lh, feasible_delay_hl)
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def run_delay_simulation(self, period, load, slew):
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@ -330,11 +330,11 @@ class delay():
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# Checking from not data_value to data_value
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self.write_delay_stimulus(period, load, slew)
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self.stim.run_sim()
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delay0 = ch.parse_output("timing", "delay0")
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delay1 = ch.parse_output("timing", "delay1")
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slew0 = ch.parse_output("timing", "slew0")
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slew1 = ch.parse_output("timing", "slew1")
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delays = (delay0, delay1, slew0, slew1)
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delay_hl = ch.parse_output("timing", "delay_hl")
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delay_lh = ch.parse_output("timing", "delay_lh")
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slew_hl = ch.parse_output("timing", "slew_hl")
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slew_lh = ch.parse_output("timing", "slew_lh")
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delays = (delay_hl, delay_lh, slew_hl, slew_lh)
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read0_power=ch.parse_output("timing", "read0_power")
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write0_power=ch.parse_output("timing", "write0_power")
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@ -348,10 +348,10 @@ class delay():
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#key=raw_input("press return to continue")
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# Scale results to ns and mw, respectively
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result = { "delay0" : delay0*1e9,
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"delay1" : delay1*1e9,
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"slew0" : slew0*1e9,
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"slew1" : slew1*1e9,
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result = { "delay_hl" : delay_hl*1e9,
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"delay_lh" : delay_lh*1e9,
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"slew_hl" : slew_hl*1e9,
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"slew_lh" : slew_lh*1e9,
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"read0_power" : read0_power*1e3,
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"read1_power" : read1_power*1e3,
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"write0_power" : write0_power*1e3,
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@ -382,46 +382,46 @@ class delay():
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#key=raw_input("press return to continue")
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return (leakage_power*1e3, trim_leakage_power*1e3)
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def check_valid_delays(self, period, load, slew, (delay0, delay1, slew0, slew1)):
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def check_valid_delays(self, period, load, slew, (delay_hl, delay_lh, slew_hl, slew_lh)):
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""" Check if the measurements are defined and if they are valid. """
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# if it failed or the read was longer than a period
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if type(delay0)!=float or type(delay1)!=float or type(slew1)!=float or type(slew0)!=float:
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debug.info(2,"Failed simulation: period {0} load {1} slew {2}, delay0={3}n delay1={4}ns slew0={5}n slew1={6}n".format(period,
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if type(delay_hl)!=float or type(delay_lh)!=float or type(slew_lh)!=float or type(slew_hl)!=float:
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debug.info(2,"Failed simulation: period {0} load {1} slew {2}, delay_hl={3}n delay_lh={4}ns slew_hl={5}n slew_lh={6}n".format(period,
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load,
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slew,
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delay0,
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delay1,
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slew0,
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slew1))
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delay_hl,
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delay_lh,
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slew_hl,
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slew_lh))
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return False
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# Scale delays to ns (they previously could have not been floats)
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delay0 *= 1e9
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delay1 *= 1e9
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slew0 *= 1e9
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slew1 *= 1e9
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if delay0>period or delay1>period or slew0>period or slew1>period:
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debug.info(2,"UNsuccessful simulation: period {0} load {1} slew {2}, delay0={3}n delay1={4}ns slew0={5}n slew1={6}n".format(period,
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delay_hl *= 1e9
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delay_lh *= 1e9
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slew_hl *= 1e9
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slew_lh *= 1e9
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if delay_hl>period or delay_lh>period or slew_hl>period or slew_lh>period:
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debug.info(2,"UNsuccessful simulation: period {0} load {1} slew {2}, delay_hl={3}n delay_lh={4}ns slew_hl={5}n slew_lh={6}n".format(period,
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load,
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slew,
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delay0,
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delay1,
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slew0,
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slew1))
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delay_hl,
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delay_lh,
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slew_hl,
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slew_lh))
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return False
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else:
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debug.info(2,"Successful simulation: period {0} load {1} slew {2}, delay0={3}n delay1={4}ns slew0={5}n slew1={6}n".format(period,
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debug.info(2,"Successful simulation: period {0} load {1} slew {2}, delay_hl={3}n delay_lh={4}ns slew_hl={5}n slew_lh={6}n".format(period,
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load,
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slew,
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delay0,
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delay1,
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slew0,
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slew1))
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delay_hl,
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delay_lh,
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slew_hl,
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slew_lh))
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return True
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def find_min_period(self,feasible_period, load, slew, feasible_delay1, feasible_delay0):
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def find_min_period(self,feasible_period, load, slew, feasible_delay_lh, feasible_delay_hl):
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"""
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Searches for the smallest period with output delays being within 5% of
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long period.
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@ -442,7 +442,7 @@ class delay():
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ub_period,
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lb_period))
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if self.try_period(target_period, load, slew, feasible_delay1, feasible_delay0):
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if self.try_period(target_period, load, slew, feasible_delay_lh, feasible_delay_hl):
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ub_period = target_period
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else:
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lb_period = target_period
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@ -452,7 +452,7 @@ class delay():
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return ub_period
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def try_period(self, period, load, slew, feasible_delay1, feasible_delay0):
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def try_period(self, period, load, slew, feasible_delay_lh, feasible_delay_hl):
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"""
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This tries to simulate a period and checks if the result
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works. If it does and the delay is within 5% still, it returns True.
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@ -461,45 +461,45 @@ class delay():
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# Checking from not data_value to data_value
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self.write_delay_stimulus(period,load,slew)
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self.stim.run_sim()
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delay0 = ch.parse_output("timing", "delay0")
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delay1 = ch.parse_output("timing", "delay1")
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slew0 = ch.parse_output("timing", "slew0")
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slew1 = ch.parse_output("timing", "slew1")
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delay_hl = ch.parse_output("timing", "delay_hl")
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delay_lh = ch.parse_output("timing", "delay_lh")
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slew_hl = ch.parse_output("timing", "slew_hl")
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slew_lh = ch.parse_output("timing", "slew_lh")
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# if it failed or the read was longer than a period
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if type(delay0)!=float or type(delay1)!=float or type(slew1)!=float or type(slew0)!=float:
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debug.info(2,"Invalid measures: Period {0}, delay0={1}ns, delay1={2}ns slew0={3}ns slew1={4}ns".format(period,
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delay0,
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delay1,
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slew0,
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slew1))
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if type(delay_hl)!=float or type(delay_lh)!=float or type(slew_lh)!=float or type(slew_hl)!=float:
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debug.info(2,"Invalid measures: Period {0}, delay_hl={1}ns, delay_lh={2}ns slew_hl={3}ns slew_lh={4}ns".format(period,
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delay_hl,
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delay_lh,
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slew_hl,
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slew_lh))
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return False
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delay0 *= 1e9
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delay1 *= 1e9
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slew0 *= 1e9
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slew1 *= 1e9
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if delay0>period or delay1>period or slew0>period or slew1>period:
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debug.info(2,"Too long delay/slew: Period {0}, delay0={1}ns, delay1={2}ns slew0={3}ns slew1={4}ns".format(period,
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delay0,
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delay1,
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slew0,
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slew1))
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delay_hl *= 1e9
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delay_lh *= 1e9
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slew_hl *= 1e9
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slew_lh *= 1e9
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if delay_hl>period or delay_lh>period or slew_hl>period or slew_lh>period:
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debug.info(2,"Too long delay/slew: Period {0}, delay_hl={1}ns, delay_lh={2}ns slew_hl={3}ns slew_lh={4}ns".format(period,
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delay_hl,
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delay_lh,
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slew_hl,
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slew_lh))
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return False
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else:
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if not ch.relative_compare(delay1,feasible_delay1,error_tolerance=0.05):
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debug.info(2,"Delay too big {0} vs {1}".format(delay1,feasible_delay1))
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if not ch.relative_compare(delay_lh,feasible_delay_lh,error_tolerance=0.05):
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debug.info(2,"Delay too big {0} vs {1}".format(delay_lh,feasible_delay_lh))
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return False
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elif not ch.relative_compare(delay0,feasible_delay0,error_tolerance=0.05):
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debug.info(2,"Delay too big {0} vs {1}".format(delay0,feasible_delay0))
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elif not ch.relative_compare(delay_hl,feasible_delay_hl,error_tolerance=0.05):
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debug.info(2,"Delay too big {0} vs {1}".format(delay_hl,feasible_delay_hl))
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return False
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#key=raw_input("press return to continue")
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debug.info(2,"Successful period {0}, delay0={1}ns, delay1={2}ns slew0={3}ns slew1={4}ns".format(period,
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delay0,
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delay1,
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slew0,
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slew1))
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debug.info(2,"Successful period {0}, delay_hl={1}ns, delay_lh={2}ns slew_hl={3}ns slew_lh={4}ns".format(period,
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delay_hl,
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delay_lh,
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slew_hl,
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slew_lh))
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return True
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def set_probe(self,probe_address, probe_data):
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@ -544,23 +544,23 @@ class delay():
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# This is for debugging a full simulation
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# debug.info(0,"Debug simulation running...")
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# target_period=50.0
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# feasible_delay1=0.059083183
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# feasible_delay0=0.17953789
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# feasible_delay_lh=0.059083183
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# feasible_delay_hl=0.17953789
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# load=1.6728
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# slew=0.04
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# self.try_period(target_period, load, slew, feasible_delay1, feasible_delay0)
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# self.try_period(target_period, load, slew, feasible_delay_lh, feasible_delay_hl)
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# sys.exit(1)
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# 1) Find a feasible period and it's corresponding delays using the trimmed array.
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(feasible_period, feasible_delay1, feasible_delay0) = self.find_feasible_period(max(loads), max(slews))
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debug.check(feasible_delay1>0,"Negative delay may not be possible")
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debug.check(feasible_delay0>0,"Negative delay may not be possible")
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(feasible_period, feasible_delay_lh, feasible_delay_hl) = self.find_feasible_period(max(loads), max(slews))
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debug.check(feasible_delay_lh>0,"Negative delay may not be possible")
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debug.check(feasible_delay_hl>0,"Negative delay may not be possible")
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# 2) Measure the delay, slew and power for all slew/load pairs.
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# Make a list for each type of measurement to append results to
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char_data = {}
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for m in ["delay1", "delay0", "slew1", "slew0", "read0_power",
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for m in ["delay_lh", "delay_hl", "slew_lh", "slew_hl", "read0_power",
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"read1_power", "write0_power", "write1_power", "leakage_power"]:
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char_data[m]=[]
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full_array_leakage = {}
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@ -587,9 +587,9 @@ class delay():
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# 3) Finds the minimum period without degrading the delays by X%
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min_period = self.find_min_period(feasible_period, max(loads), max(slews), feasible_delay1, feasible_delay0)
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min_period = self.find_min_period(feasible_period, max(loads), max(slews), feasible_delay_lh, feasible_delay_hl)
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debug.check(type(min_period)==float,"Couldn't find minimum period.")
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debug.info(1, "Min Period: {0}n with a delay of {1} / {2}".format(min_period, feasible_delay1, feasible_delay0))
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debug.info(1, "Min Period: {0}n with a delay of {1} / {2}".format(min_period, feasible_delay_lh, feasible_delay_hl))
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# 4) Pack up the final measurements
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char_data["min_period"] = ch.round_time(min_period)
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@ -698,24 +698,24 @@ class delay():
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def analytical_delay(self,sram, slews, loads):
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""" Just return the analytical model results for the SRAM.
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"""
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LH_delay = []
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HL_delay = []
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LH_slew = []
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HL_slew = []
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delay_lh = []
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delay_hl = []
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slew_lh = []
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slew_hl = []
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for slew in slews:
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for load in loads:
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bank_delay = sram.analytical_delay(slew,load)
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# Convert from ps to ns
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LH_delay.append(bank_delay.delay/1e3)
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HL_delay.append(bank_delay.delay/1e3)
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LH_slew.append(bank_delay.slew/1e3)
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HL_slew.append(bank_delay.slew/1e3)
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delay_lh.append(bank_delay.delay/1e3)
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delay_hl.append(bank_delay.delay/1e3)
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slew_lh.append(bank_delay.slew/1e3)
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slew_hl.append(bank_delay.slew/1e3)
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data = {"min_period": 0,
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"delay1": LH_delay,
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"delay0": HL_delay,
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"slew1": LH_slew,
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"slew0": HL_slew,
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"delay_lh": delay_lh,
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"delay_hl": delay_hl,
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"slew_lh": slew_lh,
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"slew_hl": slew_hl,
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"read0_power": 0,
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"read1_power": 0,
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"write0_power": 0,
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@ -47,7 +47,7 @@ class timing_sram_test(openram_test):
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loads = [tech.spice["msflop_in_cap"]*4]
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slews = [tech.spice["rise_time"]*2]
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data = d.analyze(probe_address, probe_data,slews,loads)
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print data
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#print data
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if OPTS.tech_name == "freepdk45":
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golden_data = {'leakage_power': [0.0007348262],
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'delay_lh': [0.05799613],
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