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Fixed leakage and power unit test results.

This commit is contained in:
mguthaus 2018-02-23 15:20:52 -08:00
parent d88ff01792
commit f3efb5fb50
10 changed files with 272 additions and 167 deletions
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19
compiler/characterizer/delay.py
View File

@ -573,14 +573,10 @@ class delay():
for m in ["delay_lh", "delay_hl", "slew_lh", "slew_hl", "read0_power",
"read1_power", "write0_power", "write1_power", "leakage_power"]:
char_data[m]=[]
full_array_leakage = {}
trim_array_leakage = {}
for self.load in loads:
# 2a) Find the leakage power of the trimmmed and UNtrimmed arrays.
(full_leak, trim_leak)=self.run_power_simulation()
full_array_leakage[self.load]=full_leak
trim_array_leakage[self.load]=trim_leak
char_data["leakage_power"].append(full_array_leakage[self.load])
# 2a) Find the leakage power of the trimmmed and UNtrimmed arrays.
(full_array_leakage, trim_array_leakage)=self.run_power_simulation()
char_data["leakage_power"]=full_array_leakage
for self.slew in slews:
for self.load in loads:
@ -590,7 +586,7 @@ class delay():
for k,v in delay_results.items():
if "power" in k:
# Subtract partial array leakage and add full array leakage for the power measures
char_data[k].append(v - trim_array_leakage[self.load] + full_array_leakage[self.load])
char_data[k].append(v - trim_array_leakage + full_array_leakage)
else:
char_data[k].append(v)
@ -722,7 +718,7 @@ class delay():
delay_hl.append(bank_delay.delay/1e3)
slew_lh.append(bank_delay.slew/1e3)
slew_hl.append(bank_delay.slew/1e3)
data = {"min_period": 0,
"delay_lh": delay_lh,
"delay_hl": delay_hl,
@ -731,7 +727,8 @@ class delay():
"read0_power": 0,
"read1_power": 0,
"write0_power": 0,
"write1_power": 0
"write1_power": 0,
"leakage_power": 0
}
return data

2
compiler/characterizer/lib.py
View File

@ -130,7 +130,7 @@ class lib:
# Leakage is included in dynamic when macro is enabled
self.lib.write(" leakage_power () {\n")
self.lib.write(" when : \"CSb\";\n")
self.lib.write(" value : {};\n".format(np.mean(self.char_results["leakage_power"])))
self.lib.write(" value : {};\n".format(self.char_results["leakage_power"]))
self.lib.write(" }\n")
self.lib.write(" cell_leakage_power : {};\n".format(0))

4
compiler/tests/21_hspice_delay_test.py
View File

@ -51,7 +51,7 @@ class timing_sram_test(openram_test):
data = d.analyze(probe_address, probe_data,slews,loads)
#print data
if OPTS.tech_name == "freepdk45":
golden_data = {'leakage_power': [0.0006964536000000001],
golden_data = {'leakage_power': 0.0006964536000000001,
'delay_lh': [0.0573055],
'read0_power': [0.0337812],
'read1_power': [0.032946500000000004],
@ -62,7 +62,7 @@ class timing_sram_test(openram_test):
'delay_hl': [0.070554],
'slew_lh': [0.0190073]}
elif OPTS.tech_name == "scn3me_subm":
golden_data = {'leakage_power': [0.0004004581],
golden_data = {'leakage_power': 0.0004004581,
'delay_lh': [0.6538954],
'read0_power': [9.7622],
'read1_power': [9.589],

4
compiler/tests/21_ngspice_delay_test.py
View File

@ -49,7 +49,7 @@ class timing_sram_test(openram_test):
data = d.analyze(probe_address, probe_data,slews,loads)
#print data
if OPTS.tech_name == "freepdk45":
golden_data = {'leakage_power': [0.0007348262],
golden_data = {'leakage_power': 0.0007348262,
'delay_lh': [0.05799613],
'read0_power': [0.0384102],
'read1_power': [0.03279848],
@ -60,7 +60,7 @@ class timing_sram_test(openram_test):
'delay_hl': [0.3929995],
'slew_lh': [0.02160862]}
elif OPTS.tech_name == "scn3me_subm":
golden_data = {'leakage_power': [0.00142014],
golden_data = {'leakage_power': 0.00142014,
'delay_lh': [0.8018421],
'read0_power': [11.44908],
'read1_power': [11.416549999999999],

68
compiler/tests/golden/sram_2_16_1_freepdk45_TT_10V_25C.lib → compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib
View File

@ -1,4 +1,4 @@
library (sram_2_16_1_freepdk45_TT_10V_25C_lib){
library (sram_2_16_1_freepdk45_TT_1p0V_25C_lib){
delay_model : "table_lookup";
time_unit : "1ns" ;
voltage_unit : "1v" ;
@ -7,7 +7,8 @@ library (sram_2_16_1_freepdk45_TT_10V_25C_lib){
capacitive_load_unit(1 ,fF) ;
leakage_power_unit : "1mW" ;
pulling_resistance_unit :"1kohm" ;
operating_conditions(TT){
operating_conditions(OC){
process : 1.0 ;
voltage : 1.0 ;
temperature : 25;
}
@ -21,6 +22,9 @@ library (sram_2_16_1_freepdk45_TT_10V_25C_lib){
slew_lower_threshold_pct_rise : 10.0 ;
slew_upper_threshold_pct_rise : 90.0 ;
nom_voltage : 1.0;
nom_temperature : 25;
nom_process : 1.0;
default_cell_leakage_power : 0.0 ;
default_leakage_power_density : 0.0 ;
default_input_pin_cap : 1.0 ;
@ -45,7 +49,7 @@ library (sram_2_16_1_freepdk45_TT_10V_25C_lib){
index_2("0.00125, 0.005, 0.04");
}
default_operating_conditions : TT;
default_operating_conditions : OC;
type (DATA){
@ -76,10 +80,16 @@ cell (sram_2_16_1_freepdk45){
dont_touch : true;
area : 1032.3999375;
leakage_power () {
when : "CSb";
value : 0.00088149731;
}
cell_leakage_power : 0;
bus(DATA){
bus_type : DATA;
direction : inout;
max_capacitance : 1.6728;
min_capacitance : 0.052275;
three_state : "!OEb & !clk";
memory_write(){
address : ADDR;
@ -89,15 +99,6 @@ cell (sram_2_16_1_freepdk45){
address : ADDR;
}
pin(DATA[1:0]){
internal_power(){
when : "OEb & !clk";
rise_power(scalar){
values("0.0396585518889");
}
fall_power(scalar){
values("0.029840953");
}
}
timing(){
timing_type : setup_rising;
related_pin : "clk";
@ -126,15 +127,6 @@ cell (sram_2_16_1_freepdk45){
"-0.004, -0.004, -0.016");
}
}
internal_power(){
when : "!OEb & !clk";
rise_power(scalar){
values("0.0495000442222");
}
fall_power(scalar){
values("0.0549839213333");
}
}
timing(){
timing_sense : non_unate;
related_pin : "clk";
@ -149,12 +141,12 @@ cell (sram_2_16_1_freepdk45){
"0.429, 0.431, 0.439",\
"0.435, 0.436, 0.446");
}
rise_transition(CELL_TABLE) {
rise_transition(CELL_TABLE) {
values("0.013, 0.015, 0.026",\
"0.013, 0.015, 0.026",\
"0.013, 0.015, 0.026");
}
fall_transition(CELL_TABLE) {
}
fall_transition(CELL_TABLE) {
values("0.029, 0.031, 0.044",\
"0.029, 0.031, 0.044",\
"0.029, 0.031, 0.044");
@ -168,7 +160,6 @@ cell (sram_2_16_1_freepdk45){
direction : input;
capacitance : 0.2091;
max_transition : 0.04;
fanout_load : 1.000000;
pin(ADDR[3:0]){
timing(){
timing_type : setup_rising;
@ -304,6 +295,33 @@ cell (sram_2_16_1_freepdk45){
clock : true;
direction : input;
capacitance : 0.2091;
internal_power(){
when : "!CSb & clk & !WEb";
rise_power(scalar){
values("0.0173748762222");
}
fall_power(scalar){
values("0.0173748762222");
}
}
internal_power(){
when : "!CSb & !clk & WEb";
rise_power(scalar){
values("0.0261209913889");
}
fall_power(scalar){
values("0.0261209913889");
}
}
internal_power(){
when : "CSb";
rise_power(scalar){
values("0");
}
fall_power(scalar){
values("0");
}
}
timing(){
timing_type :"min_pulse_width";
related_pin : clk;

68
compiler/tests/golden/sram_2_16_1_freepdk45_TT_10V_25C_analytical.lib → compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib
View File

@ -1,4 +1,4 @@
library (sram_2_16_1_freepdk45_TT_10V_25C_lib){
library (sram_2_16_1_freepdk45_TT_1p0V_25C_lib){
delay_model : "table_lookup";
time_unit : "1ns" ;
voltage_unit : "1v" ;
@ -7,7 +7,8 @@ library (sram_2_16_1_freepdk45_TT_10V_25C_lib){
capacitive_load_unit(1 ,fF) ;
leakage_power_unit : "1mW" ;
pulling_resistance_unit :"1kohm" ;
operating_conditions(TT){
operating_conditions(OC){
process : 1.0 ;
voltage : 1.0 ;
temperature : 25;
}
@ -21,6 +22,9 @@ library (sram_2_16_1_freepdk45_TT_10V_25C_lib){
slew_lower_threshold_pct_rise : 10.0 ;
slew_upper_threshold_pct_rise : 90.0 ;
nom_voltage : 1.0;
nom_temperature : 25;
nom_process : 1.0;
default_cell_leakage_power : 0.0 ;
default_leakage_power_density : 0.0 ;
default_input_pin_cap : 1.0 ;
@ -45,7 +49,7 @@ library (sram_2_16_1_freepdk45_TT_10V_25C_lib){
index_2("0.00125, 0.005, 0.04");
}
default_operating_conditions : TT;
default_operating_conditions : OC;
type (DATA){
@ -76,10 +80,16 @@ cell (sram_2_16_1_freepdk45){
dont_touch : true;
area : 1032.3999375;
leakage_power () {
when : "CSb";
value : 0;
}
cell_leakage_power : 0;
bus(DATA){
bus_type : DATA;
direction : inout;
max_capacitance : 1.6728;
min_capacitance : 0.052275;
three_state : "!OEb & !clk";
memory_write(){
address : ADDR;
@ -89,15 +99,6 @@ cell (sram_2_16_1_freepdk45){
address : ADDR;
}
pin(DATA[1:0]){
internal_power(){
when : "OEb & !clk";
rise_power(scalar){
values("0");
}
fall_power(scalar){
values("0");
}
}
timing(){
timing_type : setup_rising;
related_pin : "clk";
@ -126,15 +127,6 @@ cell (sram_2_16_1_freepdk45){
"0.001, 0.001, 0.001");
}
}
internal_power(){
when : "!OEb & !clk";
rise_power(scalar){
values("0");
}
fall_power(scalar){
values("0");
}
}
timing(){
timing_sense : non_unate;
related_pin : "clk";
@ -149,12 +141,12 @@ cell (sram_2_16_1_freepdk45){
"0.123, 0.124, 0.133",\
"0.123, 0.124, 0.133");
}
rise_transition(CELL_TABLE) {
rise_transition(CELL_TABLE) {
values("0.006, 0.007, 0.018",\
"0.006, 0.007, 0.018",\
"0.006, 0.007, 0.018");
}
fall_transition(CELL_TABLE) {
}
fall_transition(CELL_TABLE) {
values("0.006, 0.007, 0.018",\
"0.006, 0.007, 0.018",\
"0.006, 0.007, 0.018");
@ -168,7 +160,6 @@ cell (sram_2_16_1_freepdk45){
direction : input;
capacitance : 0.2091;
max_transition : 0.04;
fanout_load : 1.000000;
pin(ADDR[3:0]){
timing(){
timing_type : setup_rising;
@ -304,6 +295,33 @@ cell (sram_2_16_1_freepdk45){
clock : true;
direction : input;
capacitance : 0.2091;
internal_power(){
when : "!CSb & clk & !WEb";
rise_power(scalar){
values("0.0");
}
fall_power(scalar){
values("0.0");
}
}
internal_power(){
when : "!CSb & !clk & WEb";
rise_power(scalar){
values("0.0");
}
fall_power(scalar){
values("0.0");
}
}
internal_power(){
when : "CSb";
rise_power(scalar){
values("0");
}
fall_power(scalar){
values("0");
}
}
timing(){
timing_type :"min_pulse_width";
related_pin : clk;

68
compiler/tests/golden/sram_2_16_1_freepdk45_TT_10V_25C_pruned.lib → compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib
View File

@ -1,4 +1,4 @@
library (sram_2_16_1_freepdk45_TT_10V_25C_lib){
library (sram_2_16_1_freepdk45_TT_1p0V_25C_lib){
delay_model : "table_lookup";
time_unit : "1ns" ;
voltage_unit : "1v" ;
@ -7,7 +7,8 @@ library (sram_2_16_1_freepdk45_TT_10V_25C_lib){
capacitive_load_unit(1 ,fF) ;
leakage_power_unit : "1mW" ;
pulling_resistance_unit :"1kohm" ;
operating_conditions(TT){
operating_conditions(OC){
process : 1.0 ;
voltage : 1.0 ;
temperature : 25;
}
@ -21,6 +22,9 @@ library (sram_2_16_1_freepdk45_TT_10V_25C_lib){
slew_lower_threshold_pct_rise : 10.0 ;
slew_upper_threshold_pct_rise : 90.0 ;
nom_voltage : 1.0;
nom_temperature : 25;
nom_process : 1.0;
default_cell_leakage_power : 0.0 ;
default_leakage_power_density : 0.0 ;
default_input_pin_cap : 1.0 ;
@ -45,7 +49,7 @@ library (sram_2_16_1_freepdk45_TT_10V_25C_lib){
index_2("0.00125, 0.005, 0.04");
}
default_operating_conditions : TT;
default_operating_conditions : OC;
type (DATA){
@ -76,10 +80,16 @@ cell (sram_2_16_1_freepdk45){
dont_touch : true;
area : 1032.3999375;
leakage_power () {
when : "CSb";
value : 0.00088149731;
}
cell_leakage_power : 0;
bus(DATA){
bus_type : DATA;
direction : inout;
max_capacitance : 1.6728;
min_capacitance : 0.052275;
three_state : "!OEb & !clk";
memory_write(){
address : ADDR;
@ -89,15 +99,6 @@ cell (sram_2_16_1_freepdk45){
address : ADDR;
}
pin(DATA[1:0]){
internal_power(){
when : "OEb & !clk";
rise_power(scalar){
values("0.03655734659");
}
fall_power(scalar){
values("0.0267123544789");
}
}
timing(){
timing_type : setup_rising;
related_pin : "clk";
@ -126,15 +127,6 @@ cell (sram_2_16_1_freepdk45){
"-0.004, -0.004, -0.016");
}
}
internal_power(){
when : "!OEb & !clk";
rise_power(scalar){
values("0.0336039323678");
}
fall_power(scalar){
values("0.03895461259");
}
}
timing(){
timing_sense : non_unate;
related_pin : "clk";
@ -149,12 +141,12 @@ cell (sram_2_16_1_freepdk45){
"0.426, 0.427, 0.436",\
"0.432, 0.433, 0.442");
}
rise_transition(CELL_TABLE) {
rise_transition(CELL_TABLE) {
values("0.013, 0.014, 0.026",\
"0.013, 0.014, 0.026",\
"0.013, 0.015, 0.026");
}
fall_transition(CELL_TABLE) {
}
fall_transition(CELL_TABLE) {
values("0.027, 0.029, 0.043",\
"0.027, 0.029, 0.043",\
"0.027, 0.029, 0.043");
@ -168,7 +160,6 @@ cell (sram_2_16_1_freepdk45){
direction : input;
capacitance : 0.2091;
max_transition : 0.04;
fanout_load : 1.000000;
pin(ADDR[3:0]){
timing(){
timing_type : setup_rising;
@ -304,6 +295,33 @@ cell (sram_2_16_1_freepdk45){
clock : true;
direction : input;
capacitance : 0.2091;
internal_power(){
when : "!CSb & clk & !WEb";
rise_power(scalar){
values("0.0158174252672");
}
fall_power(scalar){
values("0.0158174252672");
}
}
internal_power(){
when : "!CSb & !clk & WEb";
rise_power(scalar){
values("0.0181396362394");
}
fall_power(scalar){
values("0.0181396362394");
}
}
internal_power(){
when : "CSb";
rise_power(scalar){
values("0");
}
fall_power(scalar){
values("0");
}
}
timing(){
timing_type :"min_pulse_width";
related_pin : clk;

68
compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_50V_25C.lib → compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C.lib
View File

@ -1,4 +1,4 @@
library (sram_2_16_1_scn3me_subm_TT_50V_25C_lib){
library (sram_2_16_1_scn3me_subm_TT_5p0V_25C_lib){
delay_model : "table_lookup";
time_unit : "1ns" ;
voltage_unit : "1v" ;
@ -7,7 +7,8 @@ library (sram_2_16_1_scn3me_subm_TT_50V_25C_lib){
capacitive_load_unit(1 ,fF) ;
leakage_power_unit : "1mW" ;
pulling_resistance_unit :"1kohm" ;
operating_conditions(TT){
operating_conditions(OC){
process : 1.0 ;
voltage : 5.0 ;
temperature : 25;
}
@ -21,6 +22,9 @@ library (sram_2_16_1_scn3me_subm_TT_50V_25C_lib){
slew_lower_threshold_pct_rise : 10.0 ;
slew_upper_threshold_pct_rise : 90.0 ;
nom_voltage : 5.0;
nom_temperature : 25;
nom_process : 1.0;
default_cell_leakage_power : 0.0 ;
default_leakage_power_density : 0.0 ;
default_input_pin_cap : 1.0 ;
@ -45,7 +49,7 @@ library (sram_2_16_1_scn3me_subm_TT_50V_25C_lib){
index_2("0.0125, 0.05, 0.4");
}
default_operating_conditions : TT;
default_operating_conditions : OC;
type (DATA){
@ -76,10 +80,16 @@ cell (sram_2_16_1_scn3me_subm){
dont_touch : true;
area : 134589.78;
leakage_power () {
when : "CSb";
value : 0.0011563287;
}
cell_leakage_power : 0;
bus(DATA){
bus_type : DATA;
direction : inout;
max_capacitance : 78.5936;
min_capacitance : 2.45605;
three_state : "!OEb & !clk";
memory_write(){
address : ADDR;
@ -89,15 +99,6 @@ cell (sram_2_16_1_scn3me_subm){
address : ADDR;
}
pin(DATA[1:0]){
internal_power(){
when : "OEb & !clk";
rise_power(scalar){
values("11.5567013333");
}
fall_power(scalar){
values("8.11796563333");
}
}
timing(){
timing_type : setup_rising;
related_pin : "clk";
@ -126,15 +127,6 @@ cell (sram_2_16_1_scn3me_subm){
"-0.052, -0.059, -0.132");
}
}
internal_power(){
when : "!OEb & !clk";
rise_power(scalar){
values("12.0236177778");
}
fall_power(scalar){
values("10.8690056667");
}
}
timing(){
timing_sense : non_unate;
related_pin : "clk";
@ -149,12 +141,12 @@ cell (sram_2_16_1_scn3me_subm){
"0.585, 0.658, 1.259",\
"0.625, 0.697, 1.295");
}
rise_transition(CELL_TABLE) {
rise_transition(CELL_TABLE) {
values("0.154, 0.233, 1.086",\
"0.155, 0.234, 1.086",\
"0.158, 0.237, 1.086");
}
fall_transition(CELL_TABLE) {
}
fall_transition(CELL_TABLE) {
values("0.278, 0.359, 1.499",\
"0.278, 0.361, 1.499",\
"0.28, 0.367, 1.5");
@ -168,7 +160,6 @@ cell (sram_2_16_1_scn3me_subm){
direction : input;
capacitance : 9.8242;
max_transition : 0.4;
fanout_load : 1.000000;
pin(ADDR[3:0]){
timing(){
timing_type : setup_rising;
@ -304,6 +295,33 @@ cell (sram_2_16_1_scn3me_subm){
clock : true;
direction : input;
capacitance : 9.8242;
internal_power(){
when : "!CSb & clk & !WEb";
rise_power(scalar){
values("4.91866674167");
}
fall_power(scalar){
values("4.91866674167");
}
}
internal_power(){
when : "!CSb & !clk & WEb";
rise_power(scalar){
values("5.72315586111");
}
fall_power(scalar){
values("5.72315586111");
}
}
internal_power(){
when : "CSb";
rise_power(scalar){
values("0");
}
fall_power(scalar){
values("0");
}
}
timing(){
timing_type :"min_pulse_width";
related_pin : clk;

70
compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_50V_25C_analytical.lib → compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C_analytical.lib
View File

@ -1,4 +1,4 @@
library (sram_2_16_1_scn3me_subm_TT_50V_25C_lib){
library (sram_2_16_1_scn3me_subm_TT_5p0V_25C_lib){
delay_model : "table_lookup";
time_unit : "1ns" ;
voltage_unit : "1v" ;
@ -7,7 +7,8 @@ library (sram_2_16_1_scn3me_subm_TT_50V_25C_lib){
capacitive_load_unit(1 ,fF) ;
leakage_power_unit : "1mW" ;
pulling_resistance_unit :"1kohm" ;
operating_conditions(TT){
operating_conditions(OC){
process : 1.0 ;
voltage : 5.0 ;
temperature : 25;
}
@ -21,6 +22,9 @@ library (sram_2_16_1_scn3me_subm_TT_50V_25C_lib){
slew_lower_threshold_pct_rise : 10.0 ;
slew_upper_threshold_pct_rise : 90.0 ;
nom_voltage : 5.0;
nom_temperature : 25;
nom_process : 1.0;
default_cell_leakage_power : 0.0 ;
default_leakage_power_density : 0.0 ;
default_input_pin_cap : 1.0 ;
@ -45,7 +49,7 @@ library (sram_2_16_1_scn3me_subm_TT_50V_25C_lib){
index_2("0.0125, 0.05, 0.4");
}
default_operating_conditions : TT;
default_operating_conditions : OC;
type (DATA){
@ -74,12 +78,18 @@ cell (sram_2_16_1_scn3me_subm){
dont_use : true;
map_only : true;
dont_touch : true;
area : 122426.46;
area : 134589.78;
leakage_power () {
when : "CSb";
value : 0;
}
cell_leakage_power : 0;
bus(DATA){
bus_type : DATA;
direction : inout;
max_capacitance : 78.5936;
min_capacitance : 2.45605;
three_state : "!OEb & !clk";
memory_write(){
address : ADDR;
@ -89,15 +99,6 @@ cell (sram_2_16_1_scn3me_subm){
address : ADDR;
}
pin(DATA[1:0]){
internal_power(){
when : "OEb & !clk";
rise_power(scalar){
values("0");
}
fall_power(scalar){
values("0");
}
}
timing(){
timing_type : setup_rising;
related_pin : "clk";
@ -126,15 +127,6 @@ cell (sram_2_16_1_scn3me_subm){
"0.001, 0.001, 0.001");
}
}
internal_power(){
when : "!OEb & !clk";
rise_power(scalar){
values("0");
}
fall_power(scalar){
values("0");
}
}
timing(){
timing_sense : non_unate;
related_pin : "clk";
@ -149,12 +141,12 @@ cell (sram_2_16_1_scn3me_subm){
"0.556, 0.603, 1.044",\
"0.556, 0.603, 1.044");
}
rise_transition(CELL_TABLE) {
rise_transition(CELL_TABLE) {
values("0.024, 0.081, 0.61",\
"0.024, 0.081, 0.61",\
"0.024, 0.081, 0.61");
}
fall_transition(CELL_TABLE) {
}
fall_transition(CELL_TABLE) {
values("0.024, 0.081, 0.61",\
"0.024, 0.081, 0.61",\
"0.024, 0.081, 0.61");
@ -168,7 +160,6 @@ cell (sram_2_16_1_scn3me_subm){
direction : input;
capacitance : 9.8242;
max_transition : 0.4;
fanout_load : 1.000000;
pin(ADDR[3:0]){
timing(){
timing_type : setup_rising;
@ -304,6 +295,33 @@ cell (sram_2_16_1_scn3me_subm){
clock : true;
direction : input;
capacitance : 9.8242;
internal_power(){
when : "!CSb & clk & !WEb";
rise_power(scalar){
values("0.0");
}
fall_power(scalar){
values("0.0");
}
}
internal_power(){
when : "!CSb & !clk & WEb";
rise_power(scalar){
values("0.0");
}
fall_power(scalar){
values("0.0");
}
}
internal_power(){
when : "CSb";
rise_power(scalar){
values("0");
}
fall_power(scalar){
values("0");
}
}
timing(){
timing_type :"min_pulse_width";
related_pin : clk;

68
compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_50V_25C_pruned.lib → compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C_pruned.lib
View File

@ -1,4 +1,4 @@
library (sram_2_16_1_scn3me_subm_TT_50V_25C_lib){
library (sram_2_16_1_scn3me_subm_TT_5p0V_25C_lib){
delay_model : "table_lookup";
time_unit : "1ns" ;
voltage_unit : "1v" ;
@ -7,7 +7,8 @@ library (sram_2_16_1_scn3me_subm_TT_50V_25C_lib){
capacitive_load_unit(1 ,fF) ;
leakage_power_unit : "1mW" ;
pulling_resistance_unit :"1kohm" ;
operating_conditions(TT){
operating_conditions(OC){
process : 1.0 ;
voltage : 5.0 ;
temperature : 25;
}
@ -21,6 +22,9 @@ library (sram_2_16_1_scn3me_subm_TT_50V_25C_lib){
slew_lower_threshold_pct_rise : 10.0 ;
slew_upper_threshold_pct_rise : 90.0 ;
nom_voltage : 5.0;
nom_temperature : 25;
nom_process : 1.0;
default_cell_leakage_power : 0.0 ;
default_leakage_power_density : 0.0 ;
default_input_pin_cap : 1.0 ;
@ -45,7 +49,7 @@ library (sram_2_16_1_scn3me_subm_TT_50V_25C_lib){
index_2("0.0125, 0.05, 0.4");
}
default_operating_conditions : TT;
default_operating_conditions : OC;
type (DATA){
@ -76,10 +80,16 @@ cell (sram_2_16_1_scn3me_subm){
dont_touch : true;
area : 134589.78;
leakage_power () {
when : "CSb";
value : 0.0011563287;
}
cell_leakage_power : 0;
bus(DATA){
bus_type : DATA;
direction : inout;
max_capacitance : 78.5936;
min_capacitance : 2.45605;
three_state : "!OEb & !clk";
memory_write(){
address : ADDR;
@ -89,15 +99,6 @@ cell (sram_2_16_1_scn3me_subm){
address : ADDR;
}
pin(DATA[1:0]){
internal_power(){
when : "OEb & !clk";
rise_power(scalar){
values("10.4314073837");
}
fall_power(scalar){
values("7.13119680587");
}
}
timing(){
timing_type : setup_rising;
related_pin : "clk";
@ -126,15 +127,6 @@ cell (sram_2_16_1_scn3me_subm){
"-0.052, -0.059, -0.132");
}
}
internal_power(){
when : "!OEb & !clk";
rise_power(scalar){
values("9.93581495032");
}
fall_power(scalar){
values("10.0783428725");
}
}
timing(){
timing_sense : non_unate;
related_pin : "clk";
@ -149,12 +141,12 @@ cell (sram_2_16_1_scn3me_subm){
"0.576, 0.648, 1.249",\
"0.616, 0.687, 1.286");
}
rise_transition(CELL_TABLE) {
rise_transition(CELL_TABLE) {
values("0.153, 0.232, 1.084",\
"0.153, 0.233, 1.084",\
"0.156, 0.236, 1.084");
}
fall_transition(CELL_TABLE) {
}
fall_transition(CELL_TABLE) {
values("0.277, 0.36, 1.499",\
"0.277, 0.362, 1.499",\
"0.278, 0.37, 1.5");
@ -168,7 +160,6 @@ cell (sram_2_16_1_scn3me_subm){
direction : input;
capacitance : 9.8242;
max_transition : 0.4;
fanout_load : 1.000000;
pin(ADDR[3:0]){
timing(){
timing_type : setup_rising;
@ -304,6 +295,33 @@ cell (sram_2_16_1_scn3me_subm){
clock : true;
direction : input;
capacitance : 9.8242;
internal_power(){
when : "!CSb & clk & !WEb";
rise_power(scalar){
values("4.39065104738");
}
fall_power(scalar){
values("4.39065104738");
}
}
internal_power(){
when : "!CSb & !clk & WEb";
rise_power(scalar){
values("5.00353945572");
}
fall_power(scalar){
values("5.00353945572");
}
}
internal_power(){
when : "CSb";
rise_power(scalar){
values("0");
}
fall_power(scalar){
values("0");
}
}
timing(){
timing_type :"min_pulse_width";
related_pin : clk;