mirror of https://github.com/VLSIDA/OpenRAM.git
Tri gate and array supply to M2 and M3
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06c132b695
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@ -77,6 +77,16 @@ class tri_gate_array(design.design):
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height=out_pin.height())
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# Route both supplies
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for n in ["vdd", "gnd"]:
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for supply_pin in self.tri_inst[i].get_pins(n):
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pin_pos = supply_pin.center()
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self.add_via_center(layers=("metal2", "via2", "metal3"),
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offset=pin_pos)
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self.add_layout_pin_rect_center(text=n,
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layer="metal3",
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offset=pin_pos)
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width = self.tri.width * self.columns - (self.words_per_row - 1) * self.tri.width
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en_pin = self.tri_inst[0].get_pin("en")
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@ -93,20 +103,6 @@ class tri_gate_array(design.design):
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width=width,
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height=drc["minwidth_metal1"])
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vdd_pin = self.tri_inst[0].get_pin("vdd")
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self.add_layout_pin(text="vdd",
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layer="metal1",
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offset=vdd_pin.ll().scale(0, 1),
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width=width,
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height=drc["minwidth_metal1"])
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for gnd_pin in self.tri_inst[0].get_pins("gnd"):
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if gnd_pin.layer=="metal1":
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self.add_layout_pin(text="gnd",
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layer="metal1",
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offset=gnd_pin.ll().scale(0, 1),
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width=width,
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height=drc["minwidth_metal1"])
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def analytical_delay(self, slew, load=0.0):
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Binary file not shown.
Binary file not shown.
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@ -1,6 +1,6 @@
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magic
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tech scmos
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timestamp 1517275711
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timestamp 1523484606
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<< nwell >>
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rect -2 45 38 73
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<< pwell >>
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@ -63,8 +63,6 @@ rect 16 38 20 42
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rect 25 12 29 16
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rect 28 4 32 8
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<< metal1 >>
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rect 0 65 12 69
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rect 16 65 36 69
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rect 12 61 16 65
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rect 3 53 4 61
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rect 3 42 6 53
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@ -74,25 +72,23 @@ rect 3 31 6 38
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rect 29 31 32 53
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rect 3 27 4 31
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rect 12 23 16 27
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rect 0 19 12 23
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rect 16 19 32 23
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rect 16 19 24 23
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rect 0 12 25 16
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rect 29 12 36 16
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rect 0 4 28 8
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rect 32 4 36 8
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<< m2contact >>
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rect 8 65 12 69
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rect 15 46 19 50
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rect 25 34 29 38
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rect 32 19 36 23
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rect 24 19 28 23
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<< metal2 >>
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rect 15 50 19 73
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rect 13 46 15 50
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rect 15 34 25 38
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rect 15 9 19 34
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rect 32 23 36 73
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rect 19 5 20 9
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rect 15 0 19 5
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rect 32 0 36 19
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<< m3contact >>
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rect 15 5 19 9
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<< metal3 >>
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@ -103,11 +99,10 @@ rect 14 4 20 5
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<< m3p >>
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rect 0 0 34 73
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<< labels >>
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rlabel metal2 32 0 32 0 8 gnd
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rlabel metal1 0 65 0 65 4 vdd
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rlabel metal1 0 12 0 12 3 en
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rlabel metal1 0 4 0 4 2 en_bar
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rlabel metal1 1 20 1 20 3 gnd
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rlabel metal2 16 1 16 1 1 out
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rlabel metal2 17 70 17 70 5 in
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rlabel m2contact 10 67 10 67 1 vdd
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rlabel m2contact 26 21 26 21 1 gnd
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<< end >>
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