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OpenRAM
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Use lower case names except for leaf cells and top level

This commit is contained in:
Matt Guthaus 2018-07-18 15:10:57 -07:00
parent 4a139b682d
commit 3f57853969
3 changed files with 32 additions and 29 deletions
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30
compiler/modules/bank.py
View File

@ -74,11 +74,11 @@ class bank(design.design):
def add_pins(self):
""" Adding pins for Bank module"""
for i in range(self.word_size):
self.add_pin("DOUT[{0}]".format(i),"OUT")
self.add_pin("dout[{0}]".format(i),"OUT")
for i in range(self.word_size):
self.add_pin("BANK_DIN[{0}]".format(i),"IN")
self.add_pin("bank_din[{0}]".format(i),"IN")
for i in range(self.addr_size):
self.add_pin("A[{0}]".format(i),"INPUT")
self.add_pin("addr[{0}]".format(i),"INPUT")
# For more than one bank, we have a bank select and name
# the signals gated_*.
@ -283,7 +283,7 @@ class bank(design.design):
offset=vector(0,y_offset).scale(-1,-1))
temp = []
for i in range(self.word_size):
temp.append("sa_out[{0}]".format(i))
temp.append("dout[{0}]".format(i))
if self.words_per_row == 1:
temp.append("bl[{0}]".format(i))
temp.append("br[{0}]".format(i))
@ -305,7 +305,7 @@ class bank(design.design):
temp = []
for i in range(self.word_size):
temp.append("BANK_DIN[{0}]".format(i))
temp.append("bank_din[{0}]".format(i))
for i in range(self.word_size):
if (self.words_per_row == 1):
temp.append("bl[{0}]".format(i))
@ -328,7 +328,7 @@ class bank(design.design):
for i in range(self.word_size):
temp.append("sa_out[{0}]".format(i))
for i in range(self.word_size):
temp.append("DOUT[{0}]".format(i))
temp.append("dout[{0}]".format(i))
temp.extend([self.prefix+"tri_en", self.prefix+"tri_en_bar", "vdd", "gnd"])
self.connect_inst(temp)
@ -349,7 +349,7 @@ class bank(design.design):
temp = []
for i in range(self.row_addr_size):
temp.append("A[{0}]".format(i+self.col_addr_size))
temp.append("addr[{0}]".format(i+self.col_addr_size))
for j in range(self.num_rows):
temp.append("dec_out[{0}]".format(j))
temp.extend(["vdd", "gnd"])
@ -388,7 +388,7 @@ class bank(design.design):
temp = []
for i in range(self.col_addr_size):
temp.append("A[{0}]".format(i))
temp.append("addr[{0}]".format(i))
for j in range(self.num_col_addr_lines):
temp.append("sel[{0}]".format(j))
temp.extend(["vdd", "gnd"])
@ -621,7 +621,7 @@ class bank(design.design):
""" Add pins for the sense amp output """
for i in range(self.word_size):
data_pin = self.sense_amp_array_inst.get_pin("data[{}]".format(i))
self.add_layout_pin_rect_center(text="DOUT[{}]".format(i),
self.add_layout_pin_rect_center(text="dout[{}]".format(i),
layer=data_pin.layer,
offset=data_pin.center(),
height=data_pin.height(),
@ -631,7 +631,7 @@ class bank(design.design):
""" Metal 3 routing of tri_gate output data """
for i in range(self.word_size):
data_pin = self.tri_gate_array_inst.get_pin("out[{}]".format(i))
self.add_layout_pin_rect_center(text="DOUT[{}]".format(i),
self.add_layout_pin_rect_center(text="dout[{}]".format(i),
layer=data_pin.layer,
offset=data_pin.center(),
height=data_pin.height(),
@ -644,8 +644,8 @@ class bank(design.design):
# Create inputs for the row address lines
for i in range(self.row_addr_size):
addr_idx = i + self.col_addr_size
decoder_name = "A[{}]".format(i)
addr_name = "A[{}]".format(addr_idx)
decoder_name = "addr[{}]".format(i)
addr_name = "addr[{}]".format(addr_idx)
self.copy_layout_pin(self.row_decoder_inst, decoder_name, addr_name)
@ -654,7 +654,7 @@ class bank(design.design):
for i in range(self.word_size):
data_name = "data[{}]".format(i)
din_name = "BANK_DIN[{}]".format(i)
din_name = "bank_din[{}]".format(i)
self.copy_layout_pin(self.write_driver_array_inst, data_name, din_name)
@ -693,7 +693,7 @@ class bank(design.design):
decode_names = ["Zb", "Z"]
# The Address LSB
self.copy_layout_pin(self.col_decoder_inst, "A", "A[0]")
self.copy_layout_pin(self.col_decoder_inst, "A", "addr[0]")
elif self.col_addr_size > 1:
decode_names = []
@ -702,7 +702,7 @@ class bank(design.design):
for i in range(self.col_addr_size):
decoder_name = "in[{}]".format(i)
addr_name = "A[{}]".format(i)
addr_name = "addr[{}]".format(i)
self.copy_layout_pin(self.col_decoder_inst, decoder_name, addr_name)

12
compiler/modules/hierarchical_decoder.py
View File

@ -127,7 +127,7 @@ class hierarchical_decoder(design.design):
min_x = min(min_x, -self.pre3_8.width)
input_offset=vector(min_x - self.input_routing_width,0)
input_bus_names = ["A[{0}]".format(i) for i in range(self.num_inputs)]
input_bus_names = ["addr[{0}]".format(i) for i in range(self.num_inputs)]
self.input_rails = self.create_vertical_pin_bus(layer="metal2",
pitch=self.m2_pitch,
offset=input_offset,
@ -143,7 +143,7 @@ class hierarchical_decoder(design.design):
for i in range(2):
index = pre_num * 2 + i
input_pos = self.input_rails["A[{}]".format(index)]
input_pos = self.input_rails["addr[{}]".format(index)]
in_name = "in[{}]".format(i)
decoder_pin = self.pre2x4_inst[pre_num].get_pin(in_name)
@ -160,7 +160,7 @@ class hierarchical_decoder(design.design):
for i in range(3):
index = pre_num * 3 + i + self.no_of_pre2x4 * 2
input_pos = self.input_rails["A[{}]".format(index)]
input_pos = self.input_rails["addr[{}]".format(index)]
in_name = "in[{}]".format(i)
decoder_pin = self.pre3x8_inst[pre_num].get_pin(in_name)
@ -189,7 +189,7 @@ class hierarchical_decoder(design.design):
""" Add the module pins """
for i in range(self.num_inputs):
self.add_pin("A[{0}]".format(i))
self.add_pin("addr[{0}]".format(i))
for j in range(self.rows):
self.add_pin("decode[{0}]".format(j))
@ -250,7 +250,7 @@ class hierarchical_decoder(design.design):
pins = []
for input_index in range(2):
pins.append("A[{0}]".format(input_index + index_off1))
pins.append("addr[{0}]".format(input_index + index_off1))
for output_index in range(4):
pins.append("out[{0}]".format(output_index + index_off2))
pins.extend(["vdd", "gnd"])
@ -277,7 +277,7 @@ class hierarchical_decoder(design.design):
pins = []
for input_index in range(3):
pins.append("A[{0}]".format(input_index + in_index_offset))
pins.append("addr[{0}]".format(input_index + in_index_offset))
for output_index in range(8):
pins.append("out[{0}]".format(output_index + out_index_offset))
pins.extend(["vdd", "gnd"])

19
compiler/sram_1bank.py
View File

@ -69,7 +69,8 @@ class sram_1bank(sram_base):
self.copy_layout_pin(self.control_logic_inst, n)
for i in range(self.word_size):
self.copy_layout_pin(self.bank_inst, "DOUT[{}]".format(i))
dout_name = "dout[{}]".format(i)
self.copy_layout_pin(self.bank_inst, dout_name, dout_name.upper())
# Lower address bits
for i in range(self.col_addr_size):
@ -79,7 +80,8 @@ class sram_1bank(sram_base):
self.copy_layout_pin(self.row_addr_dff_inst, "din[{}]".format(i),"ADDR[{}]".format(i+self.col_addr_size))
for i in range(self.word_size):
self.copy_layout_pin(self.data_dff_inst, "din[{}]".format(i),"DIN[{}]".format(i))
din_name = "din[{}]".format(i)
self.copy_layout_pin(self.data_dff_inst, din_name, din_name.upper())
def route(self):
""" Route a single bank SRAM """
@ -140,7 +142,7 @@ class sram_1bank(sram_base):
""" Connect the output of the row flops to the bank pins """
for i in range(self.row_addr_size):
flop_name = "dout[{}]".format(i)
bank_name = "A[{}]".format(i+self.col_addr_size)
bank_name = "addr[{}]".format(i+self.col_addr_size)
flop_pin = self.row_addr_dff_inst.get_pin(flop_name)
bank_pin = self.bank_inst.get_pin(bank_name)
flop_pos = flop_pin.center()
@ -154,7 +156,7 @@ class sram_1bank(sram_base):
def route_col_addr_dff(self):
""" Connect the output of the row flops to the bank pins """
bus_names = ["A[{}]".format(x) for x in range(self.col_addr_size)]
bus_names = ["addr[{}]".format(x) for x in range(self.col_addr_size)]
col_addr_bus_offsets = self.create_horizontal_bus(layer="metal1",
pitch=self.m1_pitch,
offset=self.col_addr_dff_inst.ul() + vector(0, self.m1_pitch),
@ -165,7 +167,7 @@ class sram_1bank(sram_base):
data_dff_map = zip(dff_names, bus_names)
self.connect_horizontal_bus(data_dff_map, self.col_addr_dff_inst, col_addr_bus_offsets)
bank_names = ["A[{}]".format(x) for x in range(self.col_addr_size)]
bank_names = ["addr[{}]".format(x) for x in range(self.col_addr_size)]
data_bank_map = zip(bank_names, bus_names)
self.connect_horizontal_bus(data_bank_map, self.bank_inst, col_addr_bus_offsets)
@ -185,7 +187,7 @@ class sram_1bank(sram_base):
data_dff_map = zip(dff_names, bus_names)
self.connect_horizontal_bus(data_dff_map, self.data_dff_inst, data_bus_offsets)
bank_names = ["BANK_DIN[{}]".format(x) for x in range(self.word_size)]
bank_names = ["bank_din[{}]".format(x) for x in range(self.word_size)]
data_bank_map = zip(bank_names, bus_names)
self.connect_horizontal_bus(data_bank_map, self.bank_inst, data_bus_offsets)
@ -200,6 +202,7 @@ class sram_1bank(sram_base):
"""
for n in self.control_logic_outputs:
pin = self.control_logic_inst.get_pin(n)
self.add_label(text=n,
layer="metal3",
offset=self.control_logic_inst.get_pin(n).center())
layer=pin.layer,
offset=pin.center())