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Added Power results to lib. 

Fixed min_period and min_pulse_width values.
  Updated lib golden files.
This commit is contained in:
Samira Ataei 2016-11-19 20:19:16 -06:00
parent eceb27cad7
commit d195df682d
4 changed files with 115 additions and 33 deletions
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8
compiler/characterizer/delay.py
View File

@ -384,10 +384,14 @@ class delay():
if (min_period0 == None) or (delay0 == None):
return None
debug.info(1, "Min Period for high_to_low transistion: {0}n with a delay of {1}".format(min_period0, delay0))
data = {"min_period1": min_period1, # period in ns
read_power=ch.convert_to_float(ch.parse_output("timing", "power_read"))
write_power=ch.convert_to_float(ch.parse_output("timing", "power_write"))
data = {"min_period1": min_period1, # period in ns
"delay1": delay1, # delay in s
"min_period0": min_period0,
"delay0": delay0
"delay0": delay0,
"Read_Power": read_power,
"Write_Power": write_power
}
return data

48
compiler/characterizer/lib.py
View File

@ -62,7 +62,7 @@ class lib:
probe_data = self.word_size - 1
data = self.d.analyze(probe_address, probe_data)
for i in data.keys():
for i in data.keys()[0:3]:
data[i] = ch.round_time(data[i])
@ -82,7 +82,7 @@ class lib:
self.lib.write(" current_unit : \"1mA\" ;\n")
self.lib.write(" resistance_unit : \"1kohm\" ;\n")
self.lib.write(" capacitive_load_unit(1 ,fF) ;\n")
self.lib.write(" leakage_power_unit : \"1uW\" ;\n")
self.lib.write(" leakage_power_unit : \"1mW\" ;\n")
self.lib.write(" pulling_resistance_unit :\"1kohm\" ;\n")
self.lib.write(" operating_conditions(TT){\n")
self.lib.write(" voltage : {0} ;\n".format(tech.spice["supply_voltage"]))
@ -144,6 +144,13 @@ class lib:
self.lib.write(" index_1 (\"0.5\");\n")
self.lib.write(" }\n\n")
CONS2 = ["INPUT_BY_TRANS_FOR_CLOCK" , "INPUT_BY_TRANS_FOR_SIGNAL"]
for i in CONS2:
self.lib.write(" power_lut_template({0})".format(i))
self.lib.write("{\n")
self.lib.write(" variable_1 : input_transition_time;\n")
self.lib.write(" index_1 (\"0.5\");\n")
self.lib.write(" }\n\n")
def write_bus(self):
""" Adds format of DATA and ADDR bus."""
@ -201,17 +208,36 @@ class lib:
self.lib.write(" pin(DATA[{0}:0])".format(self.word_size - 1))
self.lib.write("{\n")
self.lib.write(" }\n")
self.lib.write(" three_state : \"OEb & !clk\"; \n")
self.lib.write(" three_state : \"!OEb & !clk\"; \n")
self.lib.write(" memory_write(){ \n")
self.lib.write(" address : ADDR; \n")
self.lib.write(" clocked_on : clk; \n")
self.lib.write(" }\n")
self.write_timing(times)
self.lib.write(" internal_power(){\n")
self.lib.write(" when : \"OEb & !clk\"; \n")
self.lib.write(" rise_power(INPUT_BY_TRANS_FOR_SIGNAL){\n")
self.lib.write(" values(\"{0}\");\n".format(data["Write_Power"]* 1e3))
self.lib.write(" }\n")
self.lib.write(" fall_power(INPUT_BY_TRANS_FOR_SIGNAL){\n")
self.lib.write(" values(\"{0}\");\n".format(data["Write_Power"]* 1e3))
self.lib.write(" }\n")
self.lib.write(" }\n")
self.write_timing(times)
self.lib.write(" memory_read(){ \n")
self.lib.write(" address : ADDR; \n")
self.lib.write(" }\n")
self.lib.write(" timing(){ \n")
self.lib.write(" internal_power(){\n")
self.lib.write(" when : \"!OEb & !clk\"; \n")
self.lib.write(" rise_power(INPUT_BY_TRANS_FOR_SIGNAL){\n")
self.lib.write(" values(\"{0}\");\n".format(data["Read_Power"]* 1e3))
self.lib.write(" }\n")
self.lib.write(" fall_power(INPUT_BY_TRANS_FOR_SIGNAL){\n")
self.lib.write(" values(\"{0}\");\n".format(data["Read_Power"]* 1e3))
self.lib.write(" }\n")
self.lib.write(" }\n")
self.lib.write(" timing(){ \n")
self.lib.write(" timing_sense : non_unate; \n")
self.lib.write(" related_pin : \"clk\"; \n")
self.lib.write(" timing_type : rising_edge; \n")
@ -267,26 +293,26 @@ class lib:
self.lib.write(" clock : true;\n")
self.lib.write(" direction : input; \n")
self.lib.write(" capacitance : {0}; \n".format(tech.spice["FF_in_cap"]))
self.lib.write(" min_pulse_width_high : {0} ; \n".format(ch.round_time(data["min_period1"])))
self.lib.write(" min_pulse_width_low : {0} ; \n".format(ch.round_time(data["min_period0"])))
min_pulse_width = (ch.round_time(data["min_period1"]) + ch.round_time(data["min_period0"]))/2
min_period = ch.round_time(data["min_period1"]) + ch.round_time(data["min_period0"])
self.lib.write(" timing(){ \n")
self.lib.write(" timing_type :\"min_pulse_width\"; \n")
self.lib.write(" related_pin : clk; \n")
self.lib.write(" rise_constraint(CLK_TRAN) {\n")
self.lib.write(" values(\"0\"); \n")
self.lib.write(" values(\"{0}\"); \n".format(min_pulse_width))
self.lib.write(" }\n")
self.lib.write(" fall_constraint(CLK_TRAN) {\n")
self.lib.write(" values(\"0\"); \n")
self.lib.write(" values(\"{0}\"); \n".format(min_pulse_width))
self.lib.write(" }\n")
self.lib.write(" }\n")
self.lib.write(" timing(){ \n")
self.lib.write(" timing_type :\"minimum_period\"; \n")
self.lib.write(" related_pin : clk; \n")
self.lib.write(" rise_constraint(CLK_TRAN) {\n")
self.lib.write(" values(\"0\"); \n")
self.lib.write(" values(\"{0}\"); \n".format(min_period))
self.lib.write(" }\n")
self.lib.write(" fall_constraint(CLK_TRAN) {\n")
self.lib.write(" values(\"0\"); \n")
self.lib.write(" values(\"{0}\"); \n".format(min_period))
self.lib.write(" }\n")
self.lib.write(" }\n")
self.lib.write(" }\n")

50
compiler/tests/golden/sram_2_16_1_freepdk45.lib
View File

@ -5,7 +5,7 @@ library (sram_2_16_1_freepdk45_lib){
current_unit : "1mA" ;
resistance_unit : "1kohm" ;
capacitive_load_unit(1 ,fF) ;
leakage_power_unit : "1uW" ;
leakage_power_unit : "1mW" ;
pulling_resistance_unit :"1kohm" ;
operating_conditions(TT){
voltage : 1.0 ;
@ -69,6 +69,16 @@ library (sram_2_16_1_freepdk45_lib){
index_1 ("0.5");
}
power_lut_template(INPUT_BY_TRANS_FOR_CLOCK){
variable_1 : input_transition_time;
index_1 ("0.5");
}
power_lut_template(INPUT_BY_TRANS_FOR_SIGNAL){
variable_1 : input_transition_time;
index_1 ("0.5");
}
default_operating_conditions : TT;
@ -106,11 +116,20 @@ cell (sram_2_16_1_freepdk45){
max_capacitance : 0.62166;
pin(DATA[1:0]){
}
three_state : "OEb & !clk";
three_state : "!OEb & !clk";
memory_write(){
address : ADDR;
clocked_on : clk;
}
internal_power(){
when : "OEb & !clk";
rise_power(INPUT_BY_TRANS_FOR_SIGNAL){
values("0.6942568");
}
fall_power(INPUT_BY_TRANS_FOR_SIGNAL){
values("0.6942568");
}
}
timing(){
timing_type : setup_rising;
related_pin : "clk";
@ -134,21 +153,30 @@ cell (sram_2_16_1_freepdk45){
memory_read(){
address : ADDR;
}
internal_power(){
when : "!OEb & !clk";
rise_power(INPUT_BY_TRANS_FOR_SIGNAL){
values("0.0290396");
}
fall_power(INPUT_BY_TRANS_FOR_SIGNAL){
values("0.0290396");
}
}
timing(){
timing_sense : non_unate;
related_pin : "clk";
timing_type : rising_edge;
cell_rise(CELL_UP_FOR_CLOCK) {
values("0.042");
values("0.061");
}
cell_fall(CELL_DN_FOR_CLOCK) {
values("0.241");
values("0.24");
}
rise_transition(TRAN) {
values("0.042");
values("0.061");
}
fall_transition(TRAN) {
values("0.241");
values("0.24");
}
}
}
@ -262,26 +290,24 @@ cell (sram_2_16_1_freepdk45){
clock : true;
direction : input;
capacitance : 0.2091;
min_pulse_width_high : 0.081 ;
min_pulse_width_low : 0.267 ;
timing(){
timing_type :"min_pulse_width";
related_pin : clk;
rise_constraint(CLK_TRAN) {
values("0");
values("0.1745");
}
fall_constraint(CLK_TRAN) {
values("0");
values("0.1745");
}
}
timing(){
timing_type :"minimum_period";
related_pin : clk;
rise_constraint(CLK_TRAN) {
values("0");
values("0.349");
}
fall_constraint(CLK_TRAN) {
values("0");
values("0.349");
}
}
}

42
compiler/tests/golden/sram_2_16_1_scn3me_subm.lib
View File

@ -5,7 +5,7 @@ library (sram_2_16_1_scn3me_subm_lib){
current_unit : "1mA" ;
resistance_unit : "1kohm" ;
capacitive_load_unit(1 ,fF) ;
leakage_power_unit : "1uW" ;
leakage_power_unit : "1mW" ;
pulling_resistance_unit :"1kohm" ;
operating_conditions(TT){
voltage : 5.0 ;
@ -69,6 +69,16 @@ library (sram_2_16_1_scn3me_subm_lib){
index_1 ("0.5");
}
power_lut_template(INPUT_BY_TRANS_FOR_CLOCK){
variable_1 : input_transition_time;
index_1 ("0.5");
}
power_lut_template(INPUT_BY_TRANS_FOR_SIGNAL){
variable_1 : input_transition_time;
index_1 ("0.5");
}
default_operating_conditions : TT;
@ -106,11 +116,20 @@ cell (sram_2_16_1_scn3me_subm){
max_capacitance : 11.3222;
pin(DATA[1:0]){
}
three_state : "OEb & !clk";
three_state : "!OEb & !clk";
memory_write(){
address : ADDR;
clocked_on : clk;
}
internal_power(){
when : "OEb & !clk";
rise_power(INPUT_BY_TRANS_FOR_SIGNAL){
values("15.6576");
}
fall_power(INPUT_BY_TRANS_FOR_SIGNAL){
values("15.6576");
}
}
timing(){
timing_type : setup_rising;
related_pin : "clk";
@ -134,6 +153,15 @@ cell (sram_2_16_1_scn3me_subm){
memory_read(){
address : ADDR;
}
internal_power(){
when : "!OEb & !clk";
rise_power(INPUT_BY_TRANS_FOR_SIGNAL){
values("6.2822");
}
fall_power(INPUT_BY_TRANS_FOR_SIGNAL){
values("6.2822");
}
}
timing(){
timing_sense : non_unate;
related_pin : "clk";
@ -262,26 +290,24 @@ cell (sram_2_16_1_scn3me_subm){
clock : true;
direction : input;
capacitance : 9.8242;
min_pulse_width_high : 1.658 ;
min_pulse_width_low : 3.428 ;
timing(){
timing_type :"min_pulse_width";
related_pin : clk;
rise_constraint(CLK_TRAN) {
values("0");
values("2.543");
}
fall_constraint(CLK_TRAN) {
values("0");
values("2.543");
}
}
timing(){
timing_type :"minimum_period";
related_pin : clk;
rise_constraint(CLK_TRAN) {
values("0");
values("5.086");
}
fall_constraint(CLK_TRAN) {
values("0");
values("5.086");
}
}
}