mirror of https://github.com/VLSIDA/OpenRAM.git
Add area/perimeter of source/drain to transistor netlist. Gets rid of some spice warnings, gives better non-annotated measurements.
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941094ce31
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33b04bbca5
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@ -63,10 +63,15 @@ class ptx(design.design):
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# self.spice.append("\n.SUBCKT {0} {1}".format(self.name,
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# " ".join(self.pins)))
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self.spice_device="M{{0}} {{1}} {0} m={1} w={2}u l={3}u".format(spice[self.tx_type],
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self.mults,
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self.tx_width,
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drc["minwidth_poly"])
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# Just make a guess since these will actually be decided in the layout later.
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area_sd = 2.5*drc["minwidth_poly"]*self.tx_width
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perimeter_sd = 2*drc["minwidth_poly"] + 2*self.tx_width
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self.spice_device="M{{0}} {{1}} {0} m={1} w={2}u l={3}u pd={4}u ps={4}u as={5}p ad={5}p".format(spice[self.tx_type],
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self.mults,
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self.tx_width,
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drc["minwidth_poly"],
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perimeter_sd,
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area_sd)
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self.spice.append("\n* ptx " + self.spice_device)
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# self.spice.append(".ENDS {0}".format(self.name))
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@ -124,6 +124,8 @@ def write_netgen_script(cell_name, sp_name):
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f.write("flatten class {{{0}.spice precharge_array}}\n".format(cell_name))
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f.write("property {{{0}.spice nfet}} remove as ad ps pd\n".format(cell_name))
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f.write("property {{{0}.spice pfet}} remove as ad ps pd\n".format(cell_name))
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f.write("property {{{0} n}} remove as ad ps pd\n".format(sp_name))
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f.write("property {{{0} p}} remove as ad ps pd\n".format(sp_name))
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# Allow some flexibility in W size because magic will snap to a lambda grid
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# This can also cause disconnects unfortunately!
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# f.write("property {{{0}{1}.spice nfet}} tolerance {{w 0.1}}\n".format(OPTS.openram_temp,
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