mirror of https://github.com/VLSIDA/OpenRAM.git
Added member functions to bitcell.py and pbitcell.py for use in bitcell_array.py. bitcell_array now used only one function for every type of bitcell.
This commit is contained in:
Michael Timothy Grimes
parent
65735c08e2
commit
0cc077598e
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@ -34,3 +34,26 @@ class bitcell(design.design):
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c_para = spice["min_tx_drain_c"]
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result = self.cal_delay_with_rc(r = r, c = c_para+load, slew = slew, swing = swing)
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return result
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def list_bitcell_pins(self, col, row):
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# Creates a list of connections in the bitcell, indexed by column and row, for instance use in bitcell_array
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bitcell_pins = ["bl[{0}]".format(col),
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"br[{0}]".format(col),
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"wl[{0}]".format(row),
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"vdd",
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"gnd"]
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return bitcell_pins
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def list_row_pins(self):
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# Creates a list of row pins
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row_pins = ["WL"]
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return row_pins
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def list_column_pins(self):
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# Creates a list of column pins
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column_pins = ["BL", "BR"]
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return column_pins
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@ -30,47 +30,25 @@ class bitcell_array(design.design):
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self.height = self.row_size*self.cell.height + drc["well_enclosure_active"]
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self.width = self.column_size*self.cell.width
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if(OPTS.bitcell == "pbitcell"):
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self.add_multiport_pins()
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else:
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self.add_pins()
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self.add_pins()
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self.create_layout()
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if(OPTS.bitcell == "pbitcell"):
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self.add_multiport_layout_pins()
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else:
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self.add_layout_pins()
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self.add_layout_pins()
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self.DRC_LVS()
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def add_pins(self):
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row_list = self.cell.list_row_pins()
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column_list = self.cell.list_column_pins()
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for col in range(self.column_size):
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self.add_pin("bl[{0}]".format(col))
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self.add_pin("br[{0}]".format(col))
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for cell_column in column_list:
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self.add_pin(cell_column+"[{0}]".format(col))
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for row in range(self.row_size):
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self.add_pin("wl[{0}]".format(row))
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for cell_row in row_list:
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self.add_pin(cell_row+"[{0}]".format(row))
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self.add_pin("vdd")
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self.add_pin("gnd")
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def add_multiport_pins(self):
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self.num_write = self.cell.num_write
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self.num_read = self.cell.num_read
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for col in range(self.column_size):
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for k in range(self.num_write):
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self.add_pin("wbl{0}[{1}]".format(k,col))
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self.add_pin("wbl_bar{0}[{1}]".format(k,col))
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for k in range(self.num_read):
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self.add_pin("rbl{0}[{1}]".format(k,col))
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self.add_pin("rbl_bar{0}[{1}]".format(k,col))
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for row in range(self.row_size):
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for k in range(self.num_write):
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self.add_pin("wrow{0}[{1}]".format(k,row))
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for k in range(self.num_read):
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self.add_pin("rrow{0}[{1}]".format(k,row))
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self.add_pin("vdd")
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self.add_pin("gnd")
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def create_layout(self):
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xoffset = 0.0
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@ -86,43 +64,17 @@ class bitcell_array(design.design):
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else:
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tempy = yoffset
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dir_key = ""
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if(OPTS.bitcell == "pbitcell"):
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bitcell_nets = []
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for k in range(self.num_write):
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bitcell_nets.append("wbl{0}[{1}]".format(k,col))
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bitcell_nets.append("wbl_bar{0}[{1}]".format(k,col))
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for k in range(self.num_read):
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bitcell_nets.append("rbl{0}[{1}]".format(k,col))
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bitcell_nets.append("rbl_bar{0}[{1}]".format(k,col))
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for k in range(self.num_write):
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bitcell_nets.append("wrow{0}[{1}]".format(k,row))
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for k in range(self.num_read):
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bitcell_nets.append("rrow{0}[{1}]".format(k,row))
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bitcell_nets.append("vdd")
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bitcell_nets.append("gnd")
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self.cell_inst[row,col]=self.add_inst(name=name,
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mod=self.cell,
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offset=[xoffset, tempy],
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mirror=dir_key)
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self.connect_inst(bitcell_nets)
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else:
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self.cell_inst[row,col]=self.add_inst(name=name,
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mod=self.cell,
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offset=[xoffset, tempy],
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mirror=dir_key)
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self.connect_inst(["bl[{0}]".format(col),
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"br[{0}]".format(col),
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"wl[{0}]".format(row),
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"vdd",
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"gnd"])
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self.cell_inst[row,col]=self.add_inst(name=name,
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mod=self.cell,
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offset=[xoffset, tempy],
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mirror=dir_key)
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self.connect_inst(self.cell.list_bitcell_pins(col, row))
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yoffset += self.cell.height
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xoffset += self.cell.width
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def add_layout_pins(self):
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# Our cells have multiple gnd pins for now.
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@ -147,21 +99,19 @@ class bitcell_array(design.design):
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# overlapping cells
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full_width = self.width - 2*lower_x
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row_list = self.cell.list_row_pins()
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column_list = self.cell.list_column_pins()
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offset = vector(0.0, 0.0)
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for col in range(self.column_size):
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# get the pin of the lower row cell and make it the full width
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bl_pin = self.cell_inst[0,col].get_pin("BL")
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br_pin = self.cell_inst[0,col].get_pin("BR")
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self.add_layout_pin(text="bl[{0}]".format(col),
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layer="metal2",
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offset=bl_pin.ll(),
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width=bl_pin.width(),
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height=full_height)
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self.add_layout_pin(text="br[{0}]".format(col),
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layer="metal2",
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offset=br_pin.ll(),
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width=br_pin.width(),
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height=full_height)
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# get the pins of the lower row cell and make it the full width
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for cell_column in column_list:
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bl_pin = self.cell_inst[0,col].get_pin(cell_column)
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self.add_layout_pin(text=cell_column+"[{0}]".format(col),
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layer="metal2",
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offset=bl_pin.ll(),
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width=bl_pin.width(),
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height=full_height)
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# gnd offset is 0 in our cell, but it be non-zero
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gnd_pins = self.cell_inst[0,col].get_pins("gnd")
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@ -180,112 +130,17 @@ class bitcell_array(design.design):
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offset.x = 0.0
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for row in range(self.row_size):
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wl_pin = self.cell_inst[row,0].get_pin("WL")
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vdd_pins = self.cell_inst[row,0].get_pins("vdd")
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gnd_pins = self.cell_inst[row,0].get_pins("gnd")
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for gnd_pin in gnd_pins:
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if gnd_pin.layer=="metal1":
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self.add_layout_pin(text="gnd",
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layer="metal1",
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offset=gnd_pin.ll(),
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width=full_width,
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height=drc["minwidth_metal1"])
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# add vdd label and offset
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# only add to even rows to avoid duplicates
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for vdd_pin in vdd_pins:
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if row % 2 == 0 and vdd_pin.layer=="metal1":
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self.add_layout_pin(text="vdd",
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layer="metal1",
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offset=vdd_pin.ll(),
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width=full_width,
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height=drc["minwidth_metal1"])
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# add wl label and offset
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self.add_layout_pin(text="wl[{0}]".format(row),
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layer="metal1",
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offset=wl_pin.ll(),
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width=full_width,
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height=wl_pin.height())
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# increments to the next row height
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offset.y += self.cell.height
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def add_multiport_layout_pins(self):
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# Our cells have multiple gnd pins for now.
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# FIXME: fix for multiple vdd too
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vdd_pin = self.cell.get_pin("vdd")
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# shift it up by the overlap amount (gnd_pin) too
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# must find the lower gnd pin to determine this overlap
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lower_y = self.cell.height
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gnd_pins = self.cell.get_pins("gnd")
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for gnd_pin in gnd_pins:
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if gnd_pin.layer=="metal2" and gnd_pin.by()<lower_y:
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lower_y=gnd_pin.by()
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# lower_y is negative, so subtract off double this amount for each pair of
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# overlapping cells
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full_height = self.height - 2*lower_y
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vdd_pin = self.cell.get_pin("vdd")
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lower_x = vdd_pin.lx()
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# lower_x is negative, so subtract off double this amount for each pair of
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# overlapping cells
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full_width = self.width - 2*lower_x
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offset = vector(0.0, 0.0)
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for col in range(self.column_size):
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# get the pin of the lower row cell and make it the full width
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for k in range(self.num_write):
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wbl_pin = self.cell_inst[0,col].get_pin("wbl{0}".format(k))
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self.add_layout_pin(text="wbl{0}[{1}]".format(k,col),
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layer="metal2",
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offset=wbl_pin.ll(),
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width=wbl_pin.width(),
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height=full_height)
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wbl_bar_pin = self.cell_inst[0,col].get_pin("wbl_bar{0}".format(k))
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self.add_layout_pin(text="wbl_bar{0}[{1}]".format(k,col),
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layer="metal2",
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offset=wbl_bar_pin.ll(),
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width=wbl_bar_pin.width(),
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height=full_height)
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for k in range(self.num_read):
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rbl_pin = self.cell_inst[0,col].get_pin("rbl{0}".format(k))
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self.add_layout_pin(text="rbl{0}[{1}]".format(k,col),
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layer="metal2",
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offset=rbl_pin.ll(),
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width=rbl_pin.width(),
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height=full_height)
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rbl_bar_pin = self.cell_inst[0,col].get_pin("rbl_bar{0}".format(k))
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self.add_layout_pin(text="rbl_bar{0}[{1}]".format(k,col),
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layer="metal2",
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offset=rbl_bar_pin.ll(),
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width=rbl_bar_pin.width(),
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height=full_height)
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# gnd offset is 0 in our cell, but it be non-zero
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gnd_pins = self.cell_inst[0,col].get_pins("gnd")
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for gnd_pin in gnd_pins:
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# avoid duplicates by only doing even rows
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# also skip if it isn't the pin that spans the entire cell down to the bottom
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if gnd_pin.layer=="metal2" and gnd_pin.by()==lower_y:
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self.add_layout_pin(text="gnd",
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layer="metal2",
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offset=gnd_pin.ll(),
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width=gnd_pin.width(),
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height=full_height)
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# increments to the next column width
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offset.x += self.cell.width
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offset.x = 0.0
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for row in range(self.row_size):
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vdd_pins = self.cell_inst[row,0].get_pins("vdd")
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gnd_pins = self.cell_inst[row,0].get_pins("gnd")
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# add wl label and offset
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for cell_row in row_list:
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wl_pin = self.cell_inst[row,0].get_pin(cell_row)
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self.add_layout_pin(text=cell_row+"[{0}]".format(row),
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layer="metal1",
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offset=wl_pin.ll(),
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width=full_width,
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height=wl_pin.height())
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for gnd_pin in gnd_pins:
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if gnd_pin.layer=="metal1":
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@ -304,23 +159,6 @@ class bitcell_array(design.design):
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offset=vdd_pin.ll(),
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width=full_width,
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height=drc["minwidth_metal1"])
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# add wl label and offset
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for k in range(self.num_write):
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wrow_pin = self.cell_inst[row,0].get_pin("wrow{0}".format(k))
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self.add_layout_pin(text="wrow{0}[{1}]".format(k,row),
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layer="metal1",
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offset=wrow_pin.ll(),
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width=full_width,
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height=wrow_pin.height())
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for k in range(self.num_read):
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rrow_pin = self.cell_inst[row,0].get_pin("rrow{0}".format(k))
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self.add_layout_pin(text="rrow{0}[{1}]".format(k,row),
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layer="metal1",
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offset=rrow_pin.ll(),
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width=full_width,
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height=rrow_pin.height())
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# increments to the next row height
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offset.y += self.cell.height
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@ -146,18 +146,21 @@ class pbitcell(pgate.pgate):
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self.rightmost_xpos = -self.leftmost_xpos
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# bottommost position = gnd height + wrow height + rrow height
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# bottommost position = gnd height + wrow height + rrow height + space needed between tiled bitcells
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array_tiling_offset = 0.5*drc["minwidth_metal2"]
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self.botmost_ypos = -self.rail_tile_height \
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- self.num_write*self.rowline_tile_height \
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- read_port_flag*(self.num_read*self.rowline_tile_height)
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- read_port_flag*(self.num_read*self.rowline_tile_height) \
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- array_tiling_offset
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# topmost position = height of the inverter + height of vdd
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self.topmost_ypos = self.inverter_nmos.active_height + self.inverter_gap + self.inverter_pmos.active_height \
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+ self.rail_tile_height
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# calculations for the cell dimensions
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array_vdd_overlap = 0.5*drc["minwidth_metal1"]
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self.width = -2*self.leftmost_xpos
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self.height = self.topmost_ypos - self.botmost_ypos + 0.5*drc["minwidth_metal2"] - 0.5*drc["minwidth_metal1"]
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self.height = self.topmost_ypos - self.botmost_ypos - array_vdd_overlap
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def add_storage(self):
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@ -618,10 +621,9 @@ class pbitcell(pgate.pgate):
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the well connections must be done piecewise to avoid pwell and nwell overlap.
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"""
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cell_well_tiling_offset = 0.5*drc["minwidth_metal2"]
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""" extend pwell to encompass entire nmos region of the cell up to the height of the inverter nmos well """
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offset = vector(self.leftmost_xpos, self.botmost_ypos - cell_well_tiling_offset)
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well_height = -self.botmost_ypos + self.inverter_nmos.cell_well_height - drc["well_enclosure_active"] + cell_well_tiling_offset
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offset = vector(self.leftmost_xpos, self.botmost_ypos)
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well_height = -self.botmost_ypos + self.inverter_nmos.cell_well_height - drc["well_enclosure_active"]
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self.add_rect(layer="pwell",
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offset=offset,
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width=self.width,
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@ -711,6 +713,49 @@ class pbitcell(pgate.pgate):
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height=drc["minwidth_tx"])
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def list_bitcell_pins(self, col, row):
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# Creates a list of connections in the bitcell, indexed by column and row, for instance use in bitcell_array
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bitcell_pins = []
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for k in range(self.num_write):
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bitcell_pins.append("wbl{0}[{1}]".format(k,col))
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bitcell_pins.append("wbl_bar{0}[{1}]".format(k,col))
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for k in range(self.num_read):
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bitcell_pins.append("rbl{0}[{1}]".format(k,col))
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bitcell_pins.append("rbl_bar{0}[{1}]".format(k,col))
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for k in range(self.num_write):
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bitcell_pins.append("wrow{0}[{1}]".format(k,row))
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for k in range(self.num_read):
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bitcell_pins.append("rrow{0}[{1}]".format(k,row))
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bitcell_pins.append("vdd")
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bitcell_pins.append("gnd")
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return bitcell_pins
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def list_row_pins(self):
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# Creates a list of row pins
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row_pins = []
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for k in range(self.num_write):
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row_pins.append("wrow{0}".format(k))
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for k in range(self.num_read):
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row_pins.append("rrow{0}".format(k))
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return row_pins
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def list_column_pins(self):
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# Creates a list of column pins
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column_pins = []
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for k in range(self.num_write):
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column_pins.append("wbl{0}".format(k))
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column_pins.append("wbl_bar{0}".format(k))
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for k in range(self.num_read):
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column_pins.append("rbl{0}".format(k))
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column_pins.append("rbl_bar{0}".format(k))
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return column_pins
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def add_fail(self):
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# for failing drc when I want to observe the gds layout
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fail_position = vector(-4*drc["minwidth_metal1"], 0) # for tiling purposes
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