mirror of https://github.com/VLSIDA/OpenRAM.git
Changing control logic names to match naming scheme for multi-port. din[0] to din0[0], s_en to s_en0, addr[0] to addr0[0], etc. Sram level should pass unit tests for single port but will not currently pass for multi-port
This commit is contained in:
Michael Timothy Grimes
parent
0f8da1510e
commit
19ca0d6c2a
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@ -133,7 +133,6 @@ class bank(design.design):
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self.add_row_decoder()
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self.add_wordline_driver()
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self.add_column_decoder()
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def compute_sizes(self):
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@ -201,7 +200,7 @@ class bank(design.design):
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self.precharge_array = [None] * self.total_read
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for k in range(self.total_read):
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self.precharge_array[k] = self.mod_precharge_array(columns=self.num_cols, BL=self.read_bl_list[k], BR=self.read_br_list[k])
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self.precharge_array[k] = self.mod_precharge_array(columns=self.num_cols, bitcell_bl=self.read_bl_list[k], bitcell_br=self.read_br_list[k])
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self.add_mod(self.precharge_array[k])
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if self.col_addr_size > 0:
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@ -521,7 +520,7 @@ class bank(design.design):
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#the column decoder (if there is one).
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write_driver_min_y_offset = self.write_driver_array_inst[0].by() - 3*self.m2_pitch
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row_decoder_min_y_offset = self.row_decoder_inst[0].by()
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if self.col_addr_size > 0:
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col_decoder_min_y_offset = self.col_decoder_inst[0].by()
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else:
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@ -575,8 +574,8 @@ class bank(design.design):
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for k in range(self.total_read):
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for i in range(self.num_cols):
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precharge_bl = self.precharge_array_inst[k].get_pin(self.read_bl_list[k]+"[{}]".format(i)).bc()
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precharge_br = self.precharge_array_inst[k].get_pin(self.read_br_list[k]+"[{}]".format(i)).bc()
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precharge_bl = self.precharge_array_inst[k].get_pin("bl[{}]".format(i)).bc()
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precharge_br = self.precharge_array_inst[k].get_pin("br[{}]".format(i)).bc()
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bitcell_bl = self.bitcell_array_inst.get_pin(self.read_bl_list[k]+"[{}]".format(i)).uc()
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bitcell_br = self.bitcell_array_inst.get_pin(self.read_br_list[k]+"[{}]".format(i)).uc()
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@ -631,7 +630,7 @@ class bank(design.design):
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self.add_path("metal2",[sense_amp_br, vector(sense_amp_br.x,yoffset),
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vector(connect_br.x,yoffset), connect_br])
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def route_sense_amp_out(self):
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""" Add pins for the sense amp output """
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for i in range(self.word_size):
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@ -100,7 +100,7 @@ class control_logic(design.design):
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# leave space for the bus plus one extra space
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self.internal_bus_width = (len(self.internal_bus_list)+1)*self.m2_pitch
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# Outputs to the bank
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self.output_list = ["s_en", "w_en", "clk_buf_bar", "clk_buf"]
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self.output_list = ["s_en0", "w_en0", "clk_buf_bar", "clk_buf"]
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self.supply_list = ["vdd", "gnd"]
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@ -231,7 +231,7 @@ class control_logic(design.design):
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mod=self.inv8,
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offset=self.s_en_offset,
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mirror=mirror)
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self.connect_inst(["pre_s_en_bar", "s_en", "vdd", "gnd"])
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self.connect_inst(["pre_s_en_bar", "s_en0", "vdd", "gnd"])
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self.row_end_inst.append(self.s_en_inst)
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@ -313,7 +313,7 @@ class control_logic(design.design):
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mod=self.inv8,
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offset=w_en_offset,
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mirror=mirror)
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self.connect_inst(["pre_w_en_bar", "w_en", "vdd", "gnd"])
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self.connect_inst(["pre_w_en_bar", "w_en0", "vdd", "gnd"])
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x_off += self.inv8.width
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self.row_end_inst.append(self.w_en_inst)
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@ -406,7 +406,7 @@ class control_logic(design.design):
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self.add_path("metal1",[self.pre_w_en_inst.get_pin("Z").center(), self.pre_w_en_bar_inst.get_pin("A").center()])
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self.add_path("metal1",[self.pre_w_en_bar_inst.get_pin("Z").center(), self.w_en_inst.get_pin("A").center()])
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self.connect_output(self.w_en_inst, "Z", "w_en")
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self.connect_output(self.w_en_inst, "Z", "w_en0")
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def route_sen(self):
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rbl_out_pos = self.rbl_inst.get_pin("out").bc()
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@ -417,7 +417,7 @@ class control_logic(design.design):
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self.add_path("metal1",[self.pre_s_en_bar_inst.get_pin("Z").center(), self.s_en_inst.get_pin("A").center()])
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self.connect_output(self.s_en_inst, "Z", "s_en")
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self.connect_output(self.s_en_inst, "Z", "s_en0")
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def route_clk(self):
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""" Route the clk and clk_buf_bar signal internally """
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@ -75,7 +75,7 @@ class sram_1bank(sram_base):
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self.copy_layout_pin(self.control_logic_inst, n)
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for i in range(self.word_size):
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dout_name = "dout[{}]".format(i)
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dout_name = "dout0[{}]".format(i)
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self.copy_layout_pin(self.bank_inst, dout_name, dout_name.upper())
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# Lower address bits
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@ -179,7 +179,7 @@ class sram_1bank(sram_base):
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""" Connect the output of the row flops to the bank pins """
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for i in range(self.row_addr_size):
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flop_name = "dout[{}]".format(i)
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bank_name = "addr[{}]".format(i+self.col_addr_size)
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bank_name = "addr0[{}]".format(i+self.col_addr_size)
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flop_pin = self.row_addr_dff_inst.get_pin(flop_name)
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bank_pin = self.bank_inst.get_pin(bank_name)
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flop_pos = flop_pin.center()
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@ -204,7 +204,7 @@ class sram_1bank(sram_base):
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data_dff_map = zip(dff_names, bus_names)
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self.connect_horizontal_bus(data_dff_map, self.col_addr_dff_inst, col_addr_bus_offsets)
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bank_names = ["addr[{}]".format(x) for x in range(self.col_addr_size)]
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bank_names = ["addr0[{}]".format(x) for x in range(self.col_addr_size)]
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data_bank_map = zip(bank_names, bus_names)
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self.connect_horizontal_bus(data_bank_map, self.bank_inst, col_addr_bus_offsets)
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@ -215,7 +215,7 @@ class sram_1bank(sram_base):
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offset = self.data_dff_inst.ul() + vector(0, self.m1_pitch)
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dff_names = ["dout[{}]".format(x) for x in range(self.word_size)]
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bank_names = ["din[{}]".format(x) for x in range(self.word_size)]
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bank_names = ["din0[{}]".format(x) for x in range(self.word_size)]
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route_map = list(zip(bank_names, dff_names))
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dff_pins = {key: self.data_dff_inst.get_pin(key) for key in dff_names }
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@ -150,7 +150,7 @@ class sram_base(design):
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""" Add the horizontal and vertical busses """
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# Vertical bus
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# The order of the control signals on the control bus:
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self.control_bus_names = ["clk_buf", "clk_buf_bar", "w_en", "s_en"]
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self.control_bus_names = ["clk_buf", "clk_buf_bar", "w_en0", "s_en0"]
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self.vert_control_bus_positions = self.create_vertical_bus(layer="metal2",
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pitch=self.m2_pitch,
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offset=self.vertical_bus_offset,
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@ -328,7 +328,7 @@ class sram_base(design):
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temp.append("A[{0}]".format(i))
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if(self.num_banks > 1):
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temp.append("bank_sel[{0}]".format(bank_num))
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temp.extend(["s_en", "w_en", "clk_buf_bar","clk_buf" , "vdd", "gnd"])
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temp.extend(["s_en0", "w_en0", "clk_buf_bar","clk_buf" , "vdd", "gnd"])
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self.connect_inst(temp)
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return bank_inst
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