mirror of https://github.com/VLSIDA/OpenRAM.git
Rotate vias in hierarchical predecodes
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@ -267,8 +267,7 @@ class hierarchical_predecode(design.design):
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""" Add a pin for each row of vdd/gnd which are must-connects next level up. """
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# Find the x offsets for where the vias/pins should be placed
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in_xoffset = self.in_inst[0].lx()
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nand_xoffset = self.nand_inst[0].lx()
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in_xoffset = self.in_inst[0].rx()
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out_xoffset = self.inv_inst[0].lx()
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for num in range(0,self.number_of_outputs):
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# this will result in duplicate polygons for rails, but who cares
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@ -285,12 +284,14 @@ class hierarchical_predecode(design.design):
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width=self.inv_inst[num].rx())
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# Add pins in two locations
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for xoffset in [in_xoffset, nand_xoffset, out_xoffset]:
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for xoffset in [in_xoffset, out_xoffset]:
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pin_pos = vector(xoffset, nand_pin.cy())
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=pin_pos)
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offset=pin_pos,
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rotate=90)
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self.add_via_center(layers=("metal2", "via2", "metal3"),
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offset=pin_pos)
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offset=pin_pos,
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rotate=90)
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self.add_layout_pin_rect_center(text=n,
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layer="metal3",
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offset=pin_pos)
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