mirror of https://github.com/VLSIDA/OpenRAM.git
editted naming convention on precharge to accommodate multiport
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@ -11,8 +11,12 @@ class precharge_array(design.design):
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of bit line columns, height is the height of the bit-cell array.
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"""
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unique_id = 1
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def __init__(self, columns, size=1, BL="bl", BR="br"):
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design.design.__init__(self, "precharge_array")
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name = "precharge_array_{}".format(precharge_array.unique_id)
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precharge_array.unique_id += 1
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design.design.__init__(self, name)
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debug.info(1, "Creating {0}".format(self.name))
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self.columns = columns
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@ -12,7 +12,11 @@ class precharge(pgate.pgate):
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This module implements the precharge bitline cell used in the design.
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"""
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unique_id = 1
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def __init__(self, name, size=1, BL="bl", BR="br"):
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name = name+"_{}".format(precharge.unique_id)
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precharge.unique_id += 1
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pgate.pgate.__init__(self, name)
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debug.info(2, "create single precharge cell: {0}".format(name))
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