mirror of https://github.com/VLSIDA/OpenRAM.git
Merge branch 'master' into router
This commit is contained in:
mguthaus
commit
16063cc9a0
|
|
@ -1,54 +0,0 @@
|
|||
|
||||
Use signal names from the technology file. Right now they are hard
|
||||
coded everywhere. For example: DATA, ADDR, etc.
|
||||
|
||||
Cell name (ms_flop) is hard coded in characterizer, pin names are hard
|
||||
coded too. This should come from the config file which dynamically
|
||||
loads the module names.
|
||||
|
||||
Autodetect ideal number of threads for hspice.
|
||||
|
||||
vdd and gnd are hard coded in some places. The names should come from
|
||||
the tech file.
|
||||
|
||||
Some modules use upper/lower via layer instead of min width DRC rule
|
||||
from tech file.
|
||||
|
||||
Fix the size of the labels in freepdk45. They are ok in scn3me_subm though.
|
||||
|
||||
Add the clock buffer internal to control logic. Simulation uses
|
||||
1-4-8-16 inverters right now. Replace simulation with simple clock
|
||||
buffer after fixing.
|
||||
|
||||
Check out the multibank organization in sram.py and bank.py to see if
|
||||
it can be reduced or made more readable.
|
||||
|
||||
Move/modify similar functions in hierarchical_predecode2x4 and
|
||||
hierarchical_predecode3x8 to hierarchical_predecode class
|
||||
|
||||
Fix stimuli.py to be more readable.
|
||||
|
||||
Change the delay measurement to be from the negative clock edge to
|
||||
remove the dependency on the clock period.
|
||||
|
||||
Remove duplicate clock inverter in MS flop.
|
||||
|
||||
Make lib file have delay relative to negedge for DATA. Must update
|
||||
timing code too.
|
||||
|
||||
Convert characterizer into a Python package
|
||||
|
||||
cal_delay_over_path functions in hierarchy_spice
|
||||
can wire as output(it only take capcitance now).
|
||||
maybe consider make rc_net a class
|
||||
|
||||
dont use dictionary in analytical model make it like vector class
|
||||
|
||||
add wire delay model for bank connection
|
||||
|
||||
#may 15
|
||||
-explain why nand_2 fail lef
|
||||
-add bank seg for delay
|
||||
-build better sense amp
|
||||
|
||||
|
||||
|
|
@ -231,26 +231,22 @@ class bank(design.design):
|
|||
#self.wordline_driver.logic_effort_sizing(self.num_cols)
|
||||
self.add_mod(self.wordline_driver)
|
||||
|
||||
self.inv = pinv(name="pinv",
|
||||
nmos_width=drc["minwidth_tx"],
|
||||
self.inv = pinv(nmos_width=drc["minwidth_tx"],
|
||||
beta=parameter["pinv_beta"],
|
||||
height=self.bitcell_height)
|
||||
self.add_mod(self.inv)
|
||||
|
||||
# 4x Inverter
|
||||
self.inv4x = pinv(name="pinv4x",
|
||||
nmos_width=4*drc["minwidth_tx"],
|
||||
self.inv4x = pinv(nmos_width=4*drc["minwidth_tx"],
|
||||
beta=parameter["pinv_beta"],
|
||||
height=self.bitcell_height)
|
||||
self.add_mod(self.inv4x)
|
||||
|
||||
self.NAND2 = nand_2(name="pnand2_x1",
|
||||
nmos_width=2*drc["minwidth_tx"],
|
||||
self.NAND2 = nand_2(nmos_width=2*drc["minwidth_tx"],
|
||||
height=self.bitcell_height)
|
||||
self.add_mod(self.NAND2)
|
||||
|
||||
self.NOR2 = nor_2(name="pnor2_x1",
|
||||
nmos_width=drc["minwidth_tx"],
|
||||
self.NOR2 = nor_2(nmos_width=drc["minwidth_tx"],
|
||||
height=self.bitcell_height)
|
||||
self.add_mod(self.NOR2)
|
||||
|
||||
|
|
|
|||
|
|
@ -448,7 +448,7 @@ def run_sim():
|
|||
|
||||
if OPTS.spice_version == "hspice":
|
||||
# TODO: Should make multithreading parameter a configuration option
|
||||
cmd = "{0} -mt 8 -i {1} -o {2}timing".format(OPTS.spice_exe,
|
||||
cmd = "{0} -mt 2 -i {1} -o {2}timing".format(OPTS.spice_exe,
|
||||
temp_stim,
|
||||
OPTS.openram_temp)
|
||||
valid_retcode=0
|
||||
|
|
|
|||
|
|
@ -42,26 +42,21 @@ class control_logic(design.design):
|
|||
self.mod_ms_flop = getattr(c, OPTS.config.ms_flop)
|
||||
self.ms_flop = self.mod_ms_flop("ms_flop")
|
||||
self.add_mod(self.ms_flop)
|
||||
self.inv = pinv(name="pinv",
|
||||
nmos_width=drc["minwidth_tx"],
|
||||
self.inv = pinv(nmos_width=drc["minwidth_tx"],
|
||||
beta=parameter["pinv_beta"])
|
||||
|
||||
self.add_mod(self.inv)
|
||||
self.nand2 = nand_2(name="nand2",
|
||||
nmos_width=2 * drc["minwidth_tx"])
|
||||
self.nand2 = nand_2(nmos_width=2 * drc["minwidth_tx"])
|
||||
self.add_mod(self.nand2)
|
||||
self.NAND3 = nand_3(name="NAND3",
|
||||
nmos_width=3 * drc["minwidth_tx"])
|
||||
self.NAND3 = nand_3(nmos_width=3 * drc["minwidth_tx"])
|
||||
self.add_mod(self.NAND3)
|
||||
|
||||
# Special gates: 4x Inverter
|
||||
self.inv4 = pinv(name="pinv4",
|
||||
nmos_width=4 * drc["minwidth_tx"],
|
||||
self.inv4 = pinv(nmos_width=4 * drc["minwidth_tx"],
|
||||
beta=parameter["pinv_beta"])
|
||||
self.add_mod(self.inv4)
|
||||
|
||||
self.nor2 = nor_2(name="nor2",
|
||||
nmos_width=drc["minwidth_tx"])
|
||||
self.nor2 = nor_2(nmos_width=drc["minwidth_tx"])
|
||||
self.add_mod(self.nor2)
|
||||
|
||||
self.msf_control = ms_flop_array(name="msf_control",
|
||||
|
|
@ -70,8 +65,8 @@ class control_logic(design.design):
|
|||
word_size=3)
|
||||
self.add_mod(self.msf_control)
|
||||
|
||||
self.replica_bitline = replica_bitline("replica_bitline",
|
||||
int(math.ceil(self.num_rows / 10.0)))
|
||||
self.replica_bitline = replica_bitline(name="replica_bitline",
|
||||
rows=int(math.ceil(self.num_rows / 10.0)))
|
||||
self.add_mod(self.replica_bitline)
|
||||
|
||||
def add_pin_labels(self):
|
||||
|
|
|
|||
|
|
@ -2,15 +2,19 @@ import hierarchy_layout
|
|||
import hierarchy_spice
|
||||
import globals
|
||||
import calibre
|
||||
import debug
|
||||
import os
|
||||
|
||||
OPTS = globals.get_opts()
|
||||
|
||||
|
||||
class design(hierarchy_spice.spice, hierarchy_layout.layout):
|
||||
"""
|
||||
Design Class for all modules to inherit the base features.
|
||||
Class consisting of a set of modules and instances of these modules
|
||||
"""
|
||||
name_map = []
|
||||
|
||||
|
||||
def __init__(self, name):
|
||||
self.gds_file = OPTS.openram_tech + "gds_lib/" + name + ".gds"
|
||||
|
|
@ -19,6 +23,21 @@ class design(hierarchy_spice.spice, hierarchy_layout.layout):
|
|||
self.name = name
|
||||
hierarchy_layout.layout.__init__(self, name)
|
||||
hierarchy_spice.spice.__init__(self, name)
|
||||
|
||||
# Check if the name already exists, if so, give an error
|
||||
# because each reference must be a unique name.
|
||||
ok_list = ['ms_flop.ms_flop', 'bitcell.bitcell', 'contact.contact',
|
||||
'ptx.ptx', 'sram.sram',
|
||||
'hierarchical_predecode2x4.hierarchical_predecode2x4',
|
||||
'hierarchical_predecode3x8.hierarchical_predecode3x8']
|
||||
if name not in design.name_map:
|
||||
design.name_map.append(name)
|
||||
elif str(self.__class__) in ok_list:
|
||||
pass
|
||||
else:
|
||||
debug.error("Duplicate layout reference name {0} of class {1}. GDS2 requires names be unique.".format(name,self.__class__),-1)
|
||||
|
||||
|
||||
|
||||
def DRC_LVS(self):
|
||||
"""Checks both DRC and LVS for a module"""
|
||||
|
|
@ -27,8 +46,8 @@ class design(hierarchy_spice.spice, hierarchy_layout.layout):
|
|||
tempgds = OPTS.openram_temp + "/temp.gds"
|
||||
self.sp_write(tempspice)
|
||||
self.gds_write(tempgds)
|
||||
assert calibre.run_drc(self.name, tempgds) == 0
|
||||
assert calibre.run_lvs(self.name, tempgds, tempspice) == 0
|
||||
debug.check(calibre.run_drc(self.name, tempgds) == 0,"DRC failed for {0}".format(self.name))
|
||||
debug.check(calibre.run_lvs(self.name, tempgds, tempspice) == 0,"LVS failed for {0}".format(self.name))
|
||||
os.remove(tempspice)
|
||||
os.remove(tempgds)
|
||||
|
||||
|
|
@ -37,7 +56,7 @@ class design(hierarchy_spice.spice, hierarchy_layout.layout):
|
|||
if OPTS.check_lvsdrc:
|
||||
tempgds = OPTS.openram_temp + "/temp.gds"
|
||||
self.gds_write(tempgds)
|
||||
assert calibre.run_drc(self.name, tempgds) == 0
|
||||
debug.check(calibre.run_drc(self.name, tempgds) == 0,"DRC failed for {0}".format(self.name))
|
||||
os.remove(tempgds)
|
||||
|
||||
def LVS(self):
|
||||
|
|
@ -47,7 +66,7 @@ class design(hierarchy_spice.spice, hierarchy_layout.layout):
|
|||
tempgds = OPTS.openram_temp + "/temp.gds"
|
||||
self.sp_write(tempspice)
|
||||
self.gds_write(tempgds)
|
||||
assert calibre.run_lvs(self.name, tempgds, tempspice) == 0
|
||||
debug.check(calibre.run_lvs(self.name, tempgds, tempspice) == 0,"LVS failed for {0}".format(self.name))
|
||||
os.remove(tempspice)
|
||||
os.remove(tempgds)
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
word_size = 1
|
||||
word_size = 2
|
||||
num_words = 16
|
||||
num_banks = 1
|
||||
|
||||
|
|
|
|||
|
|
@ -111,6 +111,7 @@ def init_openram(config_file):
|
|||
|
||||
set_calibre()
|
||||
|
||||
|
||||
def read_config(config_file):
|
||||
global OPTS
|
||||
|
||||
|
|
@ -151,6 +152,12 @@ def set_calibre():
|
|||
def end_openram():
|
||||
""" Clean up openram for a proper exit """
|
||||
cleanup_paths()
|
||||
|
||||
# Reset the static duplicate name checker for unit tests.
|
||||
# This is needed for running unit tests.
|
||||
import design
|
||||
design.design.name_map=[]
|
||||
|
||||
|
||||
def cleanup_paths():
|
||||
# we should clean up this temp directory after execution...
|
||||
|
|
@ -253,7 +260,9 @@ def set_spice():
|
|||
debug.error("{0} not found. Unable to perform characterization.".format(OPTS.spice_version),1)
|
||||
else:
|
||||
debug.error("Neither hspice/ngspice not found. Unable to perform characterization.",1)
|
||||
|
||||
|
||||
if OPTS.analytical_delay:
|
||||
debug.warning("Using analytical delay models instead of characterization.")
|
||||
|
||||
|
||||
# imports correct technology directories for testing
|
||||
|
|
|
|||
|
|
@ -19,7 +19,7 @@ class hierarchical_decoder(design.design):
|
|||
"""
|
||||
|
||||
def __init__(self, nand2_nmos_width, nand3_nmos_width, rows):
|
||||
design.design.__init__(self, "hierarchical_decoder")
|
||||
design.design.__init__(self, "hierarchical_decoder_{0}rows".format(rows))
|
||||
|
||||
c = reload(__import__(OPTS.config.bitcell))
|
||||
self.mod_bitcell = getattr(c, OPTS.config.bitcell)
|
||||
|
|
@ -59,26 +59,21 @@ class hierarchical_decoder(design.design):
|
|||
# used to shift contact when connecting to NAND3 C pin down
|
||||
self.contact_shift = (self.m1m2_via.first_layer_width - self.m1m2_via.contact_width) / 2
|
||||
|
||||
self.inv = pinv(name="pinverter",
|
||||
nmos_width=drc["minwidth_tx"],
|
||||
self.inv = pinv(nmos_width=drc["minwidth_tx"],
|
||||
beta=2,
|
||||
height=self.bitcell_height)
|
||||
self.add_mod(self.inv)
|
||||
self.nand2 = nand_2(name="pnand2",
|
||||
nmos_width=self.nand2_nmos_width,
|
||||
self.nand2 = nand_2(nmos_width=self.nand2_nmos_width,
|
||||
height=self.bitcell_height)
|
||||
self.add_mod(self.nand2)
|
||||
self.nand3 = nand_3(name="pnand3",
|
||||
nmos_width=self.nand3_nmos_width,
|
||||
self.nand3 = nand_3(nmos_width=self.nand3_nmos_width,
|
||||
height=self.bitcell_height)
|
||||
self.add_mod(self.nand3)
|
||||
|
||||
# CREATION OF PRE-DECODER
|
||||
self.pre2_4 = pre2x4(self.nand2_nmos_width,
|
||||
"pre2x4")
|
||||
self.pre2_4 = pre2x4(self.nand2_nmos_width, "pre2x4")
|
||||
self.add_mod(self.pre2_4)
|
||||
self.pre3_8 = pre3x8(self.nand3_nmos_width,
|
||||
"pre3x8")
|
||||
self.pre3_8 = pre3x8(self.nand3_nmos_width, "pre3x8")
|
||||
self.add_mod(self.pre3_8)
|
||||
|
||||
def setup_layout_offsets(self):
|
||||
|
|
|
|||
|
|
@ -34,8 +34,7 @@ class hierarchical_predecode(design.design):
|
|||
def create_modules(self):
|
||||
layer_stack = ("metal1", "via1", "metal2")
|
||||
self.m1m2_via = contact(layer_stack=layer_stack)
|
||||
self.inv = pinv(name="a_inv_1",
|
||||
nmos_width=drc["minwidth_tx"],
|
||||
self.inv = pinv(nmos_width=drc["minwidth_tx"],
|
||||
beta=2,
|
||||
height=self.bitcell_height)
|
||||
self.add_mod(self.inv)
|
||||
|
|
|
|||
|
|
@ -19,8 +19,7 @@ class hierarchical_predecode2x4(hierarchical_predecode):
|
|||
self.route()
|
||||
|
||||
def create_nand(self):
|
||||
self.nand = nand_2(name="a_nand_2",
|
||||
nmos_width=self.nmos_width,
|
||||
self.nand = nand_2(nmos_width=self.nmos_width,
|
||||
height=self.bitcell_height)
|
||||
|
||||
def set_rail_height(self):
|
||||
|
|
|
|||
|
|
@ -20,8 +20,7 @@ class hierarchical_predecode3x8(hierarchical_predecode):
|
|||
self.route()
|
||||
|
||||
def create_nand(self):
|
||||
self.nand = nand_3(name="a_nand_3",
|
||||
nmos_width=self.nmos_width,
|
||||
self.nand = nand_3(nmos_width=self.nmos_width,
|
||||
height=self.bitcell_height)
|
||||
|
||||
def set_rail_height(self):
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@ class layout:
|
|||
layout/netlist and perform LVS/DRC.
|
||||
"""
|
||||
|
||||
def __init__(self, name):
|
||||
def __init__(self, name):
|
||||
self.name = name
|
||||
self.width = None
|
||||
self.height = None
|
||||
|
|
@ -68,7 +68,7 @@ class layout:
|
|||
attr_val = getattr(self,attr_key)
|
||||
|
||||
# skip the list of things as these will be offset separately
|
||||
if (attr_key in ['objs','insts','mods','pins','conns']): continue
|
||||
if (attr_key in ['objs','insts','mods','pins','conns','name_map']): continue
|
||||
|
||||
# if is a list
|
||||
if isinstance(attr_val, list):
|
||||
|
|
|
|||
|
|
@ -53,8 +53,7 @@ class logic_effort_dc(design.design):
|
|||
|
||||
def create_module(self):
|
||||
"""add the inverters"""
|
||||
self.inv = pinv(name="delay_chain_inv",
|
||||
nmos_width=drc["minwidth_tx"],
|
||||
self.inv = pinv(nmos_width=drc["minwidth_tx"],
|
||||
route_output=False)
|
||||
self.add_mod(self.inv)
|
||||
|
||||
|
|
|
|||
|
|
@ -19,8 +19,12 @@ class nand_2(design.design):
|
|||
c = reload(__import__(OPTS.config.bitcell))
|
||||
bitcell = getattr(c, OPTS.config.bitcell)
|
||||
|
||||
def __init__(self, name, nmos_width=1, height=bitcell.chars["height"]):
|
||||
""" Constructor """
|
||||
unique_id = 1
|
||||
|
||||
def __init__(self, nmos_width=1, height=bitcell.chars["height"]):
|
||||
"""Constructor : Creates a cell for a simple 2 input nand"""
|
||||
name = "nand2_{0}".format(nand_2.unique_id)
|
||||
nand_2.unique_id += 1
|
||||
design.design.__init__(self, name)
|
||||
debug.info(2, "create nand_2 strcuture {0} with size of {1}".format(
|
||||
name, nmos_width))
|
||||
|
|
|
|||
|
|
@ -19,10 +19,12 @@ class nand_3(design.design):
|
|||
c = reload(__import__(OPTS.config.bitcell))
|
||||
bitcell = getattr(c, OPTS.config.bitcell)
|
||||
|
||||
|
||||
def __init__(self, name, nmos_width=1, height=bitcell.chars["height"]):
|
||||
"""Constructor : Creates a pcell for a simple 3_input nand"""
|
||||
|
||||
unique_id = 1
|
||||
|
||||
def __init__(self, nmos_width=1, height=bitcell.chars["height"]):
|
||||
"""Constructor : Creates a cell for a simple 3 input nand"""
|
||||
name = "nand3_{0}".format(nand_3.unique_id)
|
||||
nand_3.unique_id += 1
|
||||
design.design.__init__(self, name)
|
||||
debug.info(2, "create nand_3 strcuture {0} with size of {1}".format(name, nmos_width))
|
||||
|
||||
|
|
|
|||
|
|
@ -18,8 +18,12 @@ class nor_2(design.design):
|
|||
c = reload(__import__(OPTS.config.bitcell))
|
||||
bitcell = getattr(c, OPTS.config.bitcell)
|
||||
|
||||
def __init__(self, name, nmos_width=1, height=bitcell.chars["height"]):
|
||||
"""init function"""
|
||||
unique_id = 1
|
||||
|
||||
def __init__(self, nmos_width=1, height=bitcell.chars["height"]):
|
||||
"""Constructor : Creates a cell for a simple 2 input nor"""
|
||||
name = "nor2_{0}".format(nor_2.unique_id)
|
||||
nor_2.unique_id += 1
|
||||
design.design.__init__(self, name)
|
||||
debug.info(2, "create nand_2 strcuture {0} with size of {1}".format(name, nmos_width))
|
||||
|
||||
|
|
|
|||
|
|
@ -16,7 +16,12 @@ class pinv(design.design):
|
|||
c = reload(__import__(OPTS.config.bitcell))
|
||||
bitcell = getattr(c, OPTS.config.bitcell)
|
||||
|
||||
def __init__(self, name, nmos_width=1, beta=3, height=bitcell.chars["height"], route_output=True):
|
||||
unique_id = 1
|
||||
|
||||
def __init__(self, nmos_width=1, beta=3, height=bitcell.chars["height"], route_output=True):
|
||||
"""Constructor : Creates a cell for a simple inverter"""
|
||||
name = "pinv{0}".format(pinv.unique_id)
|
||||
pinv.unique_id += 1
|
||||
design.design.__init__(self, name)
|
||||
debug.info(2, "create pinv strcuture {0} with size of {1}".format(name, nmos_width))
|
||||
|
||||
|
|
@ -48,9 +53,9 @@ class pinv(design.design):
|
|||
|
||||
# These aren't for instantiating, but we use them to get the dimensions
|
||||
self.nwell_contact = contact.contact(layer_stack=("active", "contact", "metal1"),
|
||||
dimensions=(1, self.pmos.num_of_tacts))
|
||||
dimensions=(1, self.pmos.num_of_tacts))
|
||||
self.pwell_contact = contact.contact(layer_stack=("active", "contact", "metal1"),
|
||||
dimensions=(1, self.nmos.num_of_tacts))
|
||||
dimensions=(1, self.nmos.num_of_tacts))
|
||||
|
||||
self.extend_wells()
|
||||
self.extend_active()
|
||||
|
|
|
|||
|
|
@ -21,7 +21,8 @@ class ptx(design.design):
|
|||
self.add_pins()
|
||||
self.create_layout()
|
||||
self.create_spice()
|
||||
self.DRC()
|
||||
# for run-time, we won't check every transitor DRC independently
|
||||
#self.DRC()
|
||||
|
||||
def add_pins(self):
|
||||
self.add_pin_list(["D", "G", "S", "B"])
|
||||
|
|
|
|||
|
|
@ -96,8 +96,7 @@ class replica_bitline(design.design):
|
|||
[1, 1, 1])
|
||||
self.add_mod(self.delay_chain)
|
||||
|
||||
self.inv = pinv(name="RBL_inv",
|
||||
nmos_width=drc["minwidth_tx"])
|
||||
self.inv = pinv(nmos_width=drc["minwidth_tx"])
|
||||
self.add_mod(self.inv)
|
||||
|
||||
# These aren't for instantiating, but we use them to get the dimensions
|
||||
|
|
@ -105,8 +104,7 @@ class replica_bitline(design.design):
|
|||
self.m1m2_via = contact(layer_stack=("metal1", "via1", "metal2"))
|
||||
self.m2m3_via = contact(layer_stack=("metal2", "via2", "metal3"))
|
||||
|
||||
self.nor = nor_2(name="replica_bitline_nor2",
|
||||
nmos_width=drc["minwidth_tx"])
|
||||
self.nor = nor_2(nmos_width=drc["minwidth_tx"])
|
||||
self.add_mod(self.nor)
|
||||
|
||||
self.access_tx = ptx(width=drc["minwidth_tx"],
|
||||
|
|
|
|||
|
|
@ -26,6 +26,10 @@ class sram(design.design):
|
|||
mod_class = getattr(class_file , config_mod_name)
|
||||
setattr (self, "mod_"+mod_name, mod_class)
|
||||
|
||||
# reset the static duplicate name checker for unit tests
|
||||
# in case we create more than one SRAM
|
||||
import design
|
||||
design.design.name_map=[]
|
||||
|
||||
self.ms_flop_chars = self.mod_ms_flop.chars
|
||||
self.bitcell_chars = self.mod_bitcell.chars
|
||||
|
|
@ -157,7 +161,7 @@ class sram(design.design):
|
|||
num_words=self.num_words_per_bank,
|
||||
words_per_row=self.words_per_row,
|
||||
num_banks=self.num_banks,
|
||||
name="test_bank1")
|
||||
name="bank")
|
||||
self.add_mod(self.bank)
|
||||
|
||||
# Conditionally create the
|
||||
|
|
|
|||
|
|
@ -30,7 +30,7 @@ class nand_2_test(unittest.TestCase):
|
|||
import tech
|
||||
|
||||
debug.info(2, "Checking 2-input nand gate")
|
||||
tx = nand_2.nand_2(name="a_nand_1", nmos_width=2 * tech.drc["minwidth_tx"])
|
||||
tx = nand_2.nand_2(nmos_width=2 * tech.drc["minwidth_tx"])
|
||||
OPTS.check_lvsdrc = True
|
||||
self.local_check(tx)
|
||||
globals.end_openram()
|
||||
|
|
|
|||
|
|
@ -27,7 +27,7 @@ class nand_3_test(unittest.TestCase):
|
|||
import tech
|
||||
|
||||
debug.info(2, "Checking 3-input nand gate")
|
||||
tx = nand_3.nand_3(name="nand_3", nmos_width=3 * tech.drc["minwidth_tx"])
|
||||
tx = nand_3.nand_3(nmos_width=3 * tech.drc["minwidth_tx"])
|
||||
|
||||
OPTS.check_lvsdrc = True
|
||||
self.local_check(tx)
|
||||
|
|
|
|||
|
|
@ -29,7 +29,7 @@ class nor_2_test(unittest.TestCase):
|
|||
import tech
|
||||
|
||||
debug.info(2, "Checking 2-input nor gate")
|
||||
tx = nor_2.nor_2(name="a_nor_1", nmos_width=2 * tech.drc["minwidth_tx"])
|
||||
tx = nor_2.nor_2(nmos_width=2 * tech.drc["minwidth_tx"])
|
||||
OPTS.check_lvsdrc = True
|
||||
self.local_check(tx)
|
||||
globals.end_openram()
|
||||
|
|
|
|||
|
|
@ -26,19 +26,19 @@ class pinv_test(unittest.TestCase):
|
|||
|
||||
debug.info(2, "Checking min size inverter")
|
||||
OPTS.check_lvsdrc = False
|
||||
tx = pinv.pinv(name="a_inv_1", nmos_width=tech.drc["minwidth_tx"], beta=tech.parameter["pinv_beta"])
|
||||
tx = pinv.pinv(nmos_width=tech.drc["minwidth_tx"], beta=tech.parameter["pinv_beta"])
|
||||
OPTS.check_lvsdrc = True
|
||||
self.local_check(tx)
|
||||
|
||||
debug.info(2, "Checking 2x min size inverter")
|
||||
OPTS.check_lvsdrc = False
|
||||
tx = pinv.pinv(name="a_inv_2", nmos_width=2 * tech.drc["minwidth_tx"], beta=tech.parameter["pinv_beta"])
|
||||
tx = pinv.pinv(nmos_width=2 * tech.drc["minwidth_tx"], beta=tech.parameter["pinv_beta"])
|
||||
OPTS.check_lvsdrc = True
|
||||
self.local_check(tx)
|
||||
|
||||
debug.info(2, "Checking 5x min size inverter")
|
||||
OPTS.check_lvsdrc = False
|
||||
tx = pinv.pinv(name="a_inv_5", nmos_width=5 * tech.drc["minwidth_tx"], beta=tech.parameter["pinv_beta"])
|
||||
tx = pinv.pinv(nmos_width=5 * tech.drc["minwidth_tx"], beta=tech.parameter["pinv_beta"])
|
||||
OPTS.check_lvsdrc = True
|
||||
self.local_check(tx)
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
#!/usr/bin/env python2.7
|
||||
"""
|
||||
Run a regresion test on a thierarchy_decoder.
|
||||
Run a regresion test on a hierarchical_decoder.
|
||||
"""
|
||||
|
||||
import unittest
|
||||
|
|
@ -22,38 +22,43 @@ class hierarchical_decoder_test(unittest.TestCase):
|
|||
import hierarchical_decoder
|
||||
import tech
|
||||
|
||||
debug.info(1, "Testing sample for hierarchy_decoder")
|
||||
debug.info(1, "Testing 4 row sample for hierarchical_decoder")
|
||||
OPTS.check_lvsdrc = False
|
||||
a = hierarchical_decoder.hierarchical_decoder(
|
||||
nand2_nmos_width=2 * tech.drc["minwidth_tx"], nand3_nmos_width=3 * tech.drc["minwidth_tx"], rows=4)
|
||||
a = hierarchical_decoder.hierarchical_decoder(nand2_nmos_width=2 * tech.drc["minwidth_tx"],
|
||||
nand3_nmos_width=3 * tech.drc["minwidth_tx"],
|
||||
rows=4)
|
||||
OPTS.check_lvsdrc = True
|
||||
self.local_check(a)
|
||||
|
||||
debug.info(1, "Testing sample for hierarchy_decoder")
|
||||
debug.info(1, "Testing 8 row sample for hierarchical_decoder")
|
||||
OPTS.check_lvsdrc = False
|
||||
a = hierarchical_decoder.hierarchical_decoder(
|
||||
nand2_nmos_width=2 * tech.drc["minwidth_tx"], nand3_nmos_width=3 * tech.drc["minwidth_tx"], rows=8)
|
||||
a = hierarchical_decoder.hierarchical_decoder(nand2_nmos_width=2 * tech.drc["minwidth_tx"],
|
||||
nand3_nmos_width=3 * tech.drc["minwidth_tx"],
|
||||
rows=8)
|
||||
OPTS.check_lvsdrc = True
|
||||
self.local_check(a)
|
||||
|
||||
debug.info(1, "Testing sample for hierarchy_decoder")
|
||||
debug.info(1, "Testing 32 row sample for hierarchical_decoder")
|
||||
OPTS.check_lvsdrc = False
|
||||
a = hierarchical_decoder.hierarchical_decoder(
|
||||
nand2_nmos_width=2 * tech.drc["minwidth_tx"], nand3_nmos_width=3 * tech.drc["minwidth_tx"], rows=32)
|
||||
a = hierarchical_decoder.hierarchical_decoder(nand2_nmos_width=2 * tech.drc["minwidth_tx"],
|
||||
nand3_nmos_width=3 * tech.drc["minwidth_tx"],
|
||||
rows=32)
|
||||
OPTS.check_lvsdrc = True
|
||||
self.local_check(a)
|
||||
|
||||
debug.info(1, "Testing sample for hierarchy_decoder")
|
||||
debug.info(1, "Testing 128 row sample for hierarchical_decoder")
|
||||
OPTS.check_lvsdrc = False
|
||||
a = hierarchical_decoder.hierarchical_decoder(
|
||||
nand2_nmos_width=2 * tech.drc["minwidth_tx"], nand3_nmos_width=3 * tech.drc["minwidth_tx"], rows=128)
|
||||
a = hierarchical_decoder.hierarchical_decoder(nand2_nmos_width=2 * tech.drc["minwidth_tx"],
|
||||
nand3_nmos_width=3 * tech.drc["minwidth_tx"],
|
||||
rows=128)
|
||||
OPTS.check_lvsdrc = True
|
||||
self.local_check(a)
|
||||
|
||||
debug.info(1, "Testing sample for hierarchy_decoder")
|
||||
debug.info(1, "Testing 512 row sample for hierarchical_decoder")
|
||||
OPTS.check_lvsdrc = False
|
||||
a = hierarchical_decoder.hierarchical_decoder(
|
||||
nand2_nmos_width=2 * tech.drc["minwidth_tx"], nand3_nmos_width=3 * tech.drc["minwidth_tx"], rows=512)
|
||||
a = hierarchical_decoder.hierarchical_decoder(nand2_nmos_width=2 * tech.drc["minwidth_tx"],
|
||||
nand3_nmos_width=3 * tech.drc["minwidth_tx"],
|
||||
rows=512)
|
||||
OPTS.check_lvsdrc = True
|
||||
self.local_check(a)
|
||||
|
||||
|
|
|
|||
|
|
@ -24,13 +24,6 @@ class precharge_test(unittest.TestCase):
|
|||
import precharge_array
|
||||
import tech
|
||||
|
||||
debug.info(2, "Checking 1 column precharge")
|
||||
OPTS.check_lvsdrc = False
|
||||
pc = precharge_array.precharge_array(
|
||||
name="precharge_array", columns=1, ptx_width=tech.drc["minwidth_tx"], beta=2)
|
||||
OPTS.check_lvsdrc = True
|
||||
self.local_check(pc)
|
||||
|
||||
debug.info(2, "Checking 3 column precharge")
|
||||
OPTS.check_lvsdrc = False
|
||||
pc = precharge_array.precharge_array(
|
||||
|
|
|
|||
|
|
@ -23,11 +23,6 @@ class sense_amp_test(unittest.TestCase):
|
|||
|
||||
import sense_amp_array
|
||||
|
||||
debug.info(2, "Testing sense_amp_array for word_size=1, words_per_row=1")
|
||||
OPTS.check_lvsdrc = False
|
||||
a = sense_amp_array.sense_amp_array(word_size=1, words_per_row=1)
|
||||
OPTS.check_lvsdrc = True
|
||||
self.local_check(a)
|
||||
|
||||
debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2")
|
||||
OPTS.check_lvsdrc = False
|
||||
|
|
@ -35,12 +30,6 @@ class sense_amp_test(unittest.TestCase):
|
|||
OPTS.check_lvsdrc = True
|
||||
self.local_check(a)
|
||||
|
||||
debug.info(2, "Testing sense_amp_array for word_size=3, words_per_row=1")
|
||||
OPTS.check_lvsdrc = False
|
||||
a = sense_amp_array.sense_amp_array(word_size=3, words_per_row=1)
|
||||
OPTS.check_lvsdrc = True
|
||||
self.local_check(a)
|
||||
|
||||
globals.end_openram()
|
||||
|
||||
def local_check(self, a):
|
||||
|
|
|
|||
|
|
@ -23,12 +23,6 @@ class write_driver_test(unittest.TestCase):
|
|||
|
||||
import write_driver_array
|
||||
|
||||
debug.info(2, "Testing write_driver_array for columns=16, word_size=4")
|
||||
OPTS.check_lvsdrc = False
|
||||
a = write_driver_array.write_driver_array(columns=16, word_size=4)
|
||||
OPTS.check_lvsdrc = True
|
||||
self.local_check(a)
|
||||
|
||||
debug.info(2, "Testing write_driver_array for columns=128, word_size=128")
|
||||
OPTS.check_lvsdrc = False
|
||||
a = write_driver_array.write_driver_array(columns=16, word_size=16)
|
||||
|
|
|
|||
|
|
@ -66,7 +66,7 @@ class sram_func_test(unittest.TestCase):
|
|||
import os
|
||||
|
||||
if OPTS.spice_version == "hspice":
|
||||
cmd = "hspice -mt 36 -i {0} > {1} ".format(
|
||||
cmd = "hspice -mt 2 -i {0} > {1} ".format(
|
||||
simulator_file, result_file)
|
||||
else:
|
||||
cmd = "ngspice -b -i {0} > {1} ".format(
|
||||
|
|
|
|||
|
|
@ -29,7 +29,7 @@ class sram_func_test(unittest.TestCase):
|
|||
s = sram.sram(word_size=OPTS.config.word_size,
|
||||
num_words=OPTS.config.num_words,
|
||||
num_banks=OPTS.config.num_banks,
|
||||
name="test_sram1")
|
||||
name="sram_func_test")
|
||||
|
||||
OPTS.check_lvsdrc = True
|
||||
|
||||
|
|
|
|||
|
|
@ -4829,20 +4829,20 @@ MACRO sram_2_16_1_freepdk45
|
|||
RECT 5.915 20.2075 6.05 20.2725 ;
|
||||
RECT 5.985 18.8625 6.545 18.9275 ;
|
||||
RECT 5.985 20.2075 6.545 20.2725 ;
|
||||
RECT 6.4125 19.9575 6.4775 20.2075 ;
|
||||
RECT 6.4125 19.8425 6.4775 20.2075 ;
|
||||
RECT 6.4125 18.9275 6.4775 19.0625 ;
|
||||
RECT 6.0525 18.9275 6.1175 18.9975 ;
|
||||
RECT 6.0525 20.0925 6.1175 20.2075 ;
|
||||
RECT 6.2425 19.03 6.3075 20.0925 ;
|
||||
RECT 5.985 19.49 6.02 19.555 ;
|
||||
RECT 6.3075 19.49 6.545 19.555 ;
|
||||
RECT 6.0525 20.1175 6.1175 20.2075 ;
|
||||
RECT 6.2425 19.03 6.3075 19.9775 ;
|
||||
RECT 5.985 19.445 6.02 19.51 ;
|
||||
RECT 6.3075 19.445 6.545 19.51 ;
|
||||
RECT 6.0525 19.1325 6.1175 19.2675 ;
|
||||
RECT 6.2425 19.1325 6.3075 19.2675 ;
|
||||
RECT 6.0525 19.9575 6.1175 20.0925 ;
|
||||
RECT 6.2425 19.9575 6.3075 20.0925 ;
|
||||
RECT 6.4125 19.9575 6.4775 20.0925 ;
|
||||
RECT 6.0525 19.8425 6.1175 20.1175 ;
|
||||
RECT 6.2425 19.8425 6.3075 20.1175 ;
|
||||
RECT 6.4125 19.8425 6.4775 20.1175 ;
|
||||
RECT 6.4125 18.9975 6.4775 19.1325 ;
|
||||
RECT 6.02 19.49 6.155 19.555 ;
|
||||
RECT 6.02 19.445 6.155 19.51 ;
|
||||
RECT 6.545 18.8625 7.295 18.9275 ;
|
||||
RECT 6.545 20.2075 7.295 20.2725 ;
|
||||
RECT 7.1625 19.9575 7.2275 20.24 ;
|
||||
|
|
@ -4872,40 +4872,40 @@ MACRO sram_2_16_1_freepdk45
|
|||
RECT 6.82 19.275 6.955 19.34 ;
|
||||
RECT 7.295 18.8625 7.855 18.9275 ;
|
||||
RECT 7.295 20.2075 7.855 20.2725 ;
|
||||
RECT 7.7225 19.9575 7.7875 20.2075 ;
|
||||
RECT 7.7225 19.8425 7.7875 20.2075 ;
|
||||
RECT 7.7225 18.9275 7.7875 19.0625 ;
|
||||
RECT 7.3625 18.9275 7.4275 18.9975 ;
|
||||
RECT 7.3625 20.0925 7.4275 20.2075 ;
|
||||
RECT 7.5525 19.03 7.6175 20.0925 ;
|
||||
RECT 7.295 19.49 7.33 19.555 ;
|
||||
RECT 7.6175 19.49 7.855 19.555 ;
|
||||
RECT 7.3625 20.1175 7.4275 20.2075 ;
|
||||
RECT 7.5525 19.03 7.6175 19.9775 ;
|
||||
RECT 7.295 19.445 7.33 19.51 ;
|
||||
RECT 7.6175 19.445 7.855 19.51 ;
|
||||
RECT 7.3625 19.1325 7.4275 19.2675 ;
|
||||
RECT 7.5525 19.1325 7.6175 19.2675 ;
|
||||
RECT 7.3625 19.9575 7.4275 20.0925 ;
|
||||
RECT 7.5525 19.9575 7.6175 20.0925 ;
|
||||
RECT 7.7225 19.9575 7.7875 20.0925 ;
|
||||
RECT 7.3625 19.8425 7.4275 20.1175 ;
|
||||
RECT 7.5525 19.8425 7.6175 20.1175 ;
|
||||
RECT 7.7225 19.8425 7.7875 20.1175 ;
|
||||
RECT 7.7225 18.9975 7.7875 19.1325 ;
|
||||
RECT 7.33 19.49 7.465 19.555 ;
|
||||
RECT 7.33 19.445 7.465 19.51 ;
|
||||
RECT 6.545 19.8075 6.68 19.8725 ;
|
||||
RECT 5.5325 19.805 5.5975 19.94 ;
|
||||
RECT 5.46 21.5525 5.595 21.6175 ;
|
||||
RECT 5.915 21.5525 6.05 21.6175 ;
|
||||
RECT 5.985 21.5525 6.545 21.6175 ;
|
||||
RECT 5.985 20.2075 6.545 20.2725 ;
|
||||
RECT 6.4125 20.2725 6.4775 20.5225 ;
|
||||
RECT 6.4125 20.2725 6.4775 20.6375 ;
|
||||
RECT 6.4125 21.4175 6.4775 21.5525 ;
|
||||
RECT 6.0525 21.4825 6.1175 21.5525 ;
|
||||
RECT 6.0525 20.2725 6.1175 20.3875 ;
|
||||
RECT 6.2425 20.3875 6.3075 21.45 ;
|
||||
RECT 5.985 20.925 6.02 20.99 ;
|
||||
RECT 6.3075 20.925 6.545 20.99 ;
|
||||
RECT 6.0525 20.2725 6.1175 20.3625 ;
|
||||
RECT 6.2425 20.5025 6.3075 21.45 ;
|
||||
RECT 5.985 20.97 6.02 21.035 ;
|
||||
RECT 6.3075 20.97 6.545 21.035 ;
|
||||
RECT 6.0525 21.2825 6.1175 21.4175 ;
|
||||
RECT 6.2425 21.2825 6.3075 21.4175 ;
|
||||
RECT 6.0525 20.6775 6.1175 20.8125 ;
|
||||
RECT 6.2425 20.6775 6.3075 20.8125 ;
|
||||
RECT 6.4125 20.5225 6.4775 20.6575 ;
|
||||
RECT 6.0525 20.7425 6.1175 21.0175 ;
|
||||
RECT 6.2425 20.7425 6.3075 21.0175 ;
|
||||
RECT 6.4125 20.6375 6.4775 20.9125 ;
|
||||
RECT 6.4125 21.4825 6.4775 21.6175 ;
|
||||
RECT 6.02 21.0 6.155 21.065 ;
|
||||
RECT 6.02 21.045 6.155 21.11 ;
|
||||
RECT 6.545 21.5525 7.295 21.6175 ;
|
||||
RECT 6.545 20.2075 7.295 20.2725 ;
|
||||
RECT 7.1625 20.24 7.2275 20.5225 ;
|
||||
|
|
@ -4935,40 +4935,40 @@ MACRO sram_2_16_1_freepdk45
|
|||
RECT 6.82 21.215 6.955 21.28 ;
|
||||
RECT 7.295 21.5525 7.855 21.6175 ;
|
||||
RECT 7.295 20.2075 7.855 20.2725 ;
|
||||
RECT 7.7225 20.2725 7.7875 20.5225 ;
|
||||
RECT 7.7225 20.2725 7.7875 20.6375 ;
|
||||
RECT 7.7225 21.4175 7.7875 21.5525 ;
|
||||
RECT 7.3625 21.4825 7.4275 21.5525 ;
|
||||
RECT 7.3625 20.2725 7.4275 20.3875 ;
|
||||
RECT 7.5525 20.3875 7.6175 21.45 ;
|
||||
RECT 7.295 20.925 7.33 20.99 ;
|
||||
RECT 7.6175 20.925 7.855 20.99 ;
|
||||
RECT 7.3625 20.2725 7.4275 20.3625 ;
|
||||
RECT 7.5525 20.5025 7.6175 21.45 ;
|
||||
RECT 7.295 20.97 7.33 21.035 ;
|
||||
RECT 7.6175 20.97 7.855 21.035 ;
|
||||
RECT 7.3625 21.2825 7.4275 21.4175 ;
|
||||
RECT 7.5525 21.2825 7.6175 21.4175 ;
|
||||
RECT 7.3625 20.6775 7.4275 20.8125 ;
|
||||
RECT 7.5525 20.6775 7.6175 20.8125 ;
|
||||
RECT 7.7225 20.5225 7.7875 20.6575 ;
|
||||
RECT 7.3625 20.7425 7.4275 21.0175 ;
|
||||
RECT 7.5525 20.7425 7.6175 21.0175 ;
|
||||
RECT 7.7225 20.6375 7.7875 20.9125 ;
|
||||
RECT 7.7225 21.4825 7.7875 21.6175 ;
|
||||
RECT 7.33 21.0 7.465 21.065 ;
|
||||
RECT 7.33 21.045 7.465 21.11 ;
|
||||
RECT 6.545 20.6075 6.68 20.6725 ;
|
||||
RECT 5.5325 20.54 5.5975 20.675 ;
|
||||
RECT 5.46 22.8975 5.595 22.9625 ;
|
||||
RECT 5.915 22.8975 6.05 22.9625 ;
|
||||
RECT 5.985 21.5525 6.545 21.6175 ;
|
||||
RECT 5.985 22.8975 6.545 22.9625 ;
|
||||
RECT 6.4125 22.6475 6.4775 22.8975 ;
|
||||
RECT 6.4125 22.5325 6.4775 22.8975 ;
|
||||
RECT 6.4125 21.6175 6.4775 21.7525 ;
|
||||
RECT 6.0525 21.6175 6.1175 21.6875 ;
|
||||
RECT 6.0525 22.7825 6.1175 22.8975 ;
|
||||
RECT 6.2425 21.72 6.3075 22.7825 ;
|
||||
RECT 5.985 22.18 6.02 22.245 ;
|
||||
RECT 6.3075 22.18 6.545 22.245 ;
|
||||
RECT 6.0525 22.8075 6.1175 22.8975 ;
|
||||
RECT 6.2425 21.72 6.3075 22.6675 ;
|
||||
RECT 5.985 22.135 6.02 22.2 ;
|
||||
RECT 6.3075 22.135 6.545 22.2 ;
|
||||
RECT 6.0525 21.8225 6.1175 21.9575 ;
|
||||
RECT 6.2425 21.8225 6.3075 21.9575 ;
|
||||
RECT 6.0525 22.6475 6.1175 22.7825 ;
|
||||
RECT 6.2425 22.6475 6.3075 22.7825 ;
|
||||
RECT 6.4125 22.6475 6.4775 22.7825 ;
|
||||
RECT 6.0525 22.5325 6.1175 22.8075 ;
|
||||
RECT 6.2425 22.5325 6.3075 22.8075 ;
|
||||
RECT 6.4125 22.5325 6.4775 22.8075 ;
|
||||
RECT 6.4125 21.6875 6.4775 21.8225 ;
|
||||
RECT 6.02 22.18 6.155 22.245 ;
|
||||
RECT 6.02 22.135 6.155 22.2 ;
|
||||
RECT 6.545 21.5525 7.295 21.6175 ;
|
||||
RECT 6.545 22.8975 7.295 22.9625 ;
|
||||
RECT 7.1625 22.6475 7.2275 22.93 ;
|
||||
|
|
@ -4998,40 +4998,40 @@ MACRO sram_2_16_1_freepdk45
|
|||
RECT 6.82 21.965 6.955 22.03 ;
|
||||
RECT 7.295 21.5525 7.855 21.6175 ;
|
||||
RECT 7.295 22.8975 7.855 22.9625 ;
|
||||
RECT 7.7225 22.6475 7.7875 22.8975 ;
|
||||
RECT 7.7225 22.5325 7.7875 22.8975 ;
|
||||
RECT 7.7225 21.6175 7.7875 21.7525 ;
|
||||
RECT 7.3625 21.6175 7.4275 21.6875 ;
|
||||
RECT 7.3625 22.7825 7.4275 22.8975 ;
|
||||
RECT 7.5525 21.72 7.6175 22.7825 ;
|
||||
RECT 7.295 22.18 7.33 22.245 ;
|
||||
RECT 7.6175 22.18 7.855 22.245 ;
|
||||
RECT 7.3625 22.8075 7.4275 22.8975 ;
|
||||
RECT 7.5525 21.72 7.6175 22.6675 ;
|
||||
RECT 7.295 22.135 7.33 22.2 ;
|
||||
RECT 7.6175 22.135 7.855 22.2 ;
|
||||
RECT 7.3625 21.8225 7.4275 21.9575 ;
|
||||
RECT 7.5525 21.8225 7.6175 21.9575 ;
|
||||
RECT 7.3625 22.6475 7.4275 22.7825 ;
|
||||
RECT 7.5525 22.6475 7.6175 22.7825 ;
|
||||
RECT 7.7225 22.6475 7.7875 22.7825 ;
|
||||
RECT 7.3625 22.5325 7.4275 22.8075 ;
|
||||
RECT 7.5525 22.5325 7.6175 22.8075 ;
|
||||
RECT 7.7225 22.5325 7.7875 22.8075 ;
|
||||
RECT 7.7225 21.6875 7.7875 21.8225 ;
|
||||
RECT 7.33 22.18 7.465 22.245 ;
|
||||
RECT 7.33 22.135 7.465 22.2 ;
|
||||
RECT 6.545 22.4975 6.68 22.5625 ;
|
||||
RECT 5.5325 22.495 5.5975 22.63 ;
|
||||
RECT 5.46 24.2425 5.595 24.3075 ;
|
||||
RECT 5.915 24.2425 6.05 24.3075 ;
|
||||
RECT 5.985 24.2425 6.545 24.3075 ;
|
||||
RECT 5.985 22.8975 6.545 22.9625 ;
|
||||
RECT 6.4125 22.9625 6.4775 23.2125 ;
|
||||
RECT 6.4125 22.9625 6.4775 23.3275 ;
|
||||
RECT 6.4125 24.1075 6.4775 24.2425 ;
|
||||
RECT 6.0525 24.1725 6.1175 24.2425 ;
|
||||
RECT 6.0525 22.9625 6.1175 23.0775 ;
|
||||
RECT 6.2425 23.0775 6.3075 24.14 ;
|
||||
RECT 5.985 23.615 6.02 23.68 ;
|
||||
RECT 6.3075 23.615 6.545 23.68 ;
|
||||
RECT 6.0525 22.9625 6.1175 23.0525 ;
|
||||
RECT 6.2425 23.1925 6.3075 24.14 ;
|
||||
RECT 5.985 23.66 6.02 23.725 ;
|
||||
RECT 6.3075 23.66 6.545 23.725 ;
|
||||
RECT 6.0525 23.9725 6.1175 24.1075 ;
|
||||
RECT 6.2425 23.9725 6.3075 24.1075 ;
|
||||
RECT 6.0525 23.3675 6.1175 23.5025 ;
|
||||
RECT 6.2425 23.3675 6.3075 23.5025 ;
|
||||
RECT 6.4125 23.2125 6.4775 23.3475 ;
|
||||
RECT 6.0525 23.4325 6.1175 23.7075 ;
|
||||
RECT 6.2425 23.4325 6.3075 23.7075 ;
|
||||
RECT 6.4125 23.3275 6.4775 23.6025 ;
|
||||
RECT 6.4125 24.1725 6.4775 24.3075 ;
|
||||
RECT 6.02 23.69 6.155 23.755 ;
|
||||
RECT 6.02 23.735 6.155 23.8 ;
|
||||
RECT 6.545 24.2425 7.295 24.3075 ;
|
||||
RECT 6.545 22.8975 7.295 22.9625 ;
|
||||
RECT 7.1625 22.93 7.2275 23.2125 ;
|
||||
|
|
@ -5061,40 +5061,40 @@ MACRO sram_2_16_1_freepdk45
|
|||
RECT 6.82 23.905 6.955 23.97 ;
|
||||
RECT 7.295 24.2425 7.855 24.3075 ;
|
||||
RECT 7.295 22.8975 7.855 22.9625 ;
|
||||
RECT 7.7225 22.9625 7.7875 23.2125 ;
|
||||
RECT 7.7225 22.9625 7.7875 23.3275 ;
|
||||
RECT 7.7225 24.1075 7.7875 24.2425 ;
|
||||
RECT 7.3625 24.1725 7.4275 24.2425 ;
|
||||
RECT 7.3625 22.9625 7.4275 23.0775 ;
|
||||
RECT 7.5525 23.0775 7.6175 24.14 ;
|
||||
RECT 7.295 23.615 7.33 23.68 ;
|
||||
RECT 7.6175 23.615 7.855 23.68 ;
|
||||
RECT 7.3625 22.9625 7.4275 23.0525 ;
|
||||
RECT 7.5525 23.1925 7.6175 24.14 ;
|
||||
RECT 7.295 23.66 7.33 23.725 ;
|
||||
RECT 7.6175 23.66 7.855 23.725 ;
|
||||
RECT 7.3625 23.9725 7.4275 24.1075 ;
|
||||
RECT 7.5525 23.9725 7.6175 24.1075 ;
|
||||
RECT 7.3625 23.3675 7.4275 23.5025 ;
|
||||
RECT 7.5525 23.3675 7.6175 23.5025 ;
|
||||
RECT 7.7225 23.2125 7.7875 23.3475 ;
|
||||
RECT 7.3625 23.4325 7.4275 23.7075 ;
|
||||
RECT 7.5525 23.4325 7.6175 23.7075 ;
|
||||
RECT 7.7225 23.3275 7.7875 23.6025 ;
|
||||
RECT 7.7225 24.1725 7.7875 24.3075 ;
|
||||
RECT 7.33 23.69 7.465 23.755 ;
|
||||
RECT 7.33 23.735 7.465 23.8 ;
|
||||
RECT 6.545 23.2975 6.68 23.3625 ;
|
||||
RECT 5.5325 23.23 5.5975 23.365 ;
|
||||
RECT 5.46 25.5875 5.595 25.6525 ;
|
||||
RECT 5.915 25.5875 6.05 25.6525 ;
|
||||
RECT 5.985 24.2425 6.545 24.3075 ;
|
||||
RECT 5.985 25.5875 6.545 25.6525 ;
|
||||
RECT 6.4125 25.3375 6.4775 25.5875 ;
|
||||
RECT 6.4125 25.2225 6.4775 25.5875 ;
|
||||
RECT 6.4125 24.3075 6.4775 24.4425 ;
|
||||
RECT 6.0525 24.3075 6.1175 24.3775 ;
|
||||
RECT 6.0525 25.4725 6.1175 25.5875 ;
|
||||
RECT 6.2425 24.41 6.3075 25.4725 ;
|
||||
RECT 5.985 24.87 6.02 24.935 ;
|
||||
RECT 6.3075 24.87 6.545 24.935 ;
|
||||
RECT 6.0525 25.4975 6.1175 25.5875 ;
|
||||
RECT 6.2425 24.41 6.3075 25.3575 ;
|
||||
RECT 5.985 24.825 6.02 24.89 ;
|
||||
RECT 6.3075 24.825 6.545 24.89 ;
|
||||
RECT 6.0525 24.5125 6.1175 24.6475 ;
|
||||
RECT 6.2425 24.5125 6.3075 24.6475 ;
|
||||
RECT 6.0525 25.3375 6.1175 25.4725 ;
|
||||
RECT 6.2425 25.3375 6.3075 25.4725 ;
|
||||
RECT 6.4125 25.3375 6.4775 25.4725 ;
|
||||
RECT 6.0525 25.2225 6.1175 25.4975 ;
|
||||
RECT 6.2425 25.2225 6.3075 25.4975 ;
|
||||
RECT 6.4125 25.2225 6.4775 25.4975 ;
|
||||
RECT 6.4125 24.3775 6.4775 24.5125 ;
|
||||
RECT 6.02 24.87 6.155 24.935 ;
|
||||
RECT 6.02 24.825 6.155 24.89 ;
|
||||
RECT 6.545 24.2425 7.295 24.3075 ;
|
||||
RECT 6.545 25.5875 7.295 25.6525 ;
|
||||
RECT 7.1625 25.3375 7.2275 25.62 ;
|
||||
|
|
@ -5124,40 +5124,40 @@ MACRO sram_2_16_1_freepdk45
|
|||
RECT 6.82 24.655 6.955 24.72 ;
|
||||
RECT 7.295 24.2425 7.855 24.3075 ;
|
||||
RECT 7.295 25.5875 7.855 25.6525 ;
|
||||
RECT 7.7225 25.3375 7.7875 25.5875 ;
|
||||
RECT 7.7225 25.2225 7.7875 25.5875 ;
|
||||
RECT 7.7225 24.3075 7.7875 24.4425 ;
|
||||
RECT 7.3625 24.3075 7.4275 24.3775 ;
|
||||
RECT 7.3625 25.4725 7.4275 25.5875 ;
|
||||
RECT 7.5525 24.41 7.6175 25.4725 ;
|
||||
RECT 7.295 24.87 7.33 24.935 ;
|
||||
RECT 7.6175 24.87 7.855 24.935 ;
|
||||
RECT 7.3625 25.4975 7.4275 25.5875 ;
|
||||
RECT 7.5525 24.41 7.6175 25.3575 ;
|
||||
RECT 7.295 24.825 7.33 24.89 ;
|
||||
RECT 7.6175 24.825 7.855 24.89 ;
|
||||
RECT 7.3625 24.5125 7.4275 24.6475 ;
|
||||
RECT 7.5525 24.5125 7.6175 24.6475 ;
|
||||
RECT 7.3625 25.3375 7.4275 25.4725 ;
|
||||
RECT 7.5525 25.3375 7.6175 25.4725 ;
|
||||
RECT 7.7225 25.3375 7.7875 25.4725 ;
|
||||
RECT 7.3625 25.2225 7.4275 25.4975 ;
|
||||
RECT 7.5525 25.2225 7.6175 25.4975 ;
|
||||
RECT 7.7225 25.2225 7.7875 25.4975 ;
|
||||
RECT 7.7225 24.3775 7.7875 24.5125 ;
|
||||
RECT 7.33 24.87 7.465 24.935 ;
|
||||
RECT 7.33 24.825 7.465 24.89 ;
|
||||
RECT 6.545 25.1875 6.68 25.2525 ;
|
||||
RECT 5.5325 25.185 5.5975 25.32 ;
|
||||
RECT 5.46 26.9325 5.595 26.9975 ;
|
||||
RECT 5.915 26.9325 6.05 26.9975 ;
|
||||
RECT 5.985 26.9325 6.545 26.9975 ;
|
||||
RECT 5.985 25.5875 6.545 25.6525 ;
|
||||
RECT 6.4125 25.6525 6.4775 25.9025 ;
|
||||
RECT 6.4125 25.6525 6.4775 26.0175 ;
|
||||
RECT 6.4125 26.7975 6.4775 26.9325 ;
|
||||
RECT 6.0525 26.8625 6.1175 26.9325 ;
|
||||
RECT 6.0525 25.6525 6.1175 25.7675 ;
|
||||
RECT 6.2425 25.7675 6.3075 26.83 ;
|
||||
RECT 5.985 26.305 6.02 26.37 ;
|
||||
RECT 6.3075 26.305 6.545 26.37 ;
|
||||
RECT 6.0525 25.6525 6.1175 25.7425 ;
|
||||
RECT 6.2425 25.8825 6.3075 26.83 ;
|
||||
RECT 5.985 26.35 6.02 26.415 ;
|
||||
RECT 6.3075 26.35 6.545 26.415 ;
|
||||
RECT 6.0525 26.6625 6.1175 26.7975 ;
|
||||
RECT 6.2425 26.6625 6.3075 26.7975 ;
|
||||
RECT 6.0525 26.0575 6.1175 26.1925 ;
|
||||
RECT 6.2425 26.0575 6.3075 26.1925 ;
|
||||
RECT 6.4125 25.9025 6.4775 26.0375 ;
|
||||
RECT 6.0525 26.1225 6.1175 26.3975 ;
|
||||
RECT 6.2425 26.1225 6.3075 26.3975 ;
|
||||
RECT 6.4125 26.0175 6.4775 26.2925 ;
|
||||
RECT 6.4125 26.8625 6.4775 26.9975 ;
|
||||
RECT 6.02 26.38 6.155 26.445 ;
|
||||
RECT 6.02 26.425 6.155 26.49 ;
|
||||
RECT 6.545 26.9325 7.295 26.9975 ;
|
||||
RECT 6.545 25.5875 7.295 25.6525 ;
|
||||
RECT 7.1625 25.62 7.2275 25.9025 ;
|
||||
|
|
@ -5187,40 +5187,40 @@ MACRO sram_2_16_1_freepdk45
|
|||
RECT 6.82 26.595 6.955 26.66 ;
|
||||
RECT 7.295 26.9325 7.855 26.9975 ;
|
||||
RECT 7.295 25.5875 7.855 25.6525 ;
|
||||
RECT 7.7225 25.6525 7.7875 25.9025 ;
|
||||
RECT 7.7225 25.6525 7.7875 26.0175 ;
|
||||
RECT 7.7225 26.7975 7.7875 26.9325 ;
|
||||
RECT 7.3625 26.8625 7.4275 26.9325 ;
|
||||
RECT 7.3625 25.6525 7.4275 25.7675 ;
|
||||
RECT 7.5525 25.7675 7.6175 26.83 ;
|
||||
RECT 7.295 26.305 7.33 26.37 ;
|
||||
RECT 7.6175 26.305 7.855 26.37 ;
|
||||
RECT 7.3625 25.6525 7.4275 25.7425 ;
|
||||
RECT 7.5525 25.8825 7.6175 26.83 ;
|
||||
RECT 7.295 26.35 7.33 26.415 ;
|
||||
RECT 7.6175 26.35 7.855 26.415 ;
|
||||
RECT 7.3625 26.6625 7.4275 26.7975 ;
|
||||
RECT 7.5525 26.6625 7.6175 26.7975 ;
|
||||
RECT 7.3625 26.0575 7.4275 26.1925 ;
|
||||
RECT 7.5525 26.0575 7.6175 26.1925 ;
|
||||
RECT 7.7225 25.9025 7.7875 26.0375 ;
|
||||
RECT 7.3625 26.1225 7.4275 26.3975 ;
|
||||
RECT 7.5525 26.1225 7.6175 26.3975 ;
|
||||
RECT 7.7225 26.0175 7.7875 26.2925 ;
|
||||
RECT 7.7225 26.8625 7.7875 26.9975 ;
|
||||
RECT 7.33 26.38 7.465 26.445 ;
|
||||
RECT 7.33 26.425 7.465 26.49 ;
|
||||
RECT 6.545 25.9875 6.68 26.0525 ;
|
||||
RECT 5.5325 25.92 5.5975 26.055 ;
|
||||
RECT 5.46 28.2775 5.595 28.3425 ;
|
||||
RECT 5.915 28.2775 6.05 28.3425 ;
|
||||
RECT 5.985 26.9325 6.545 26.9975 ;
|
||||
RECT 5.985 28.2775 6.545 28.3425 ;
|
||||
RECT 6.4125 28.0275 6.4775 28.2775 ;
|
||||
RECT 6.4125 27.9125 6.4775 28.2775 ;
|
||||
RECT 6.4125 26.9975 6.4775 27.1325 ;
|
||||
RECT 6.0525 26.9975 6.1175 27.0675 ;
|
||||
RECT 6.0525 28.1625 6.1175 28.2775 ;
|
||||
RECT 6.2425 27.1 6.3075 28.1625 ;
|
||||
RECT 5.985 27.56 6.02 27.625 ;
|
||||
RECT 6.3075 27.56 6.545 27.625 ;
|
||||
RECT 6.0525 28.1875 6.1175 28.2775 ;
|
||||
RECT 6.2425 27.1 6.3075 28.0475 ;
|
||||
RECT 5.985 27.515 6.02 27.58 ;
|
||||
RECT 6.3075 27.515 6.545 27.58 ;
|
||||
RECT 6.0525 27.2025 6.1175 27.3375 ;
|
||||
RECT 6.2425 27.2025 6.3075 27.3375 ;
|
||||
RECT 6.0525 28.0275 6.1175 28.1625 ;
|
||||
RECT 6.2425 28.0275 6.3075 28.1625 ;
|
||||
RECT 6.4125 28.0275 6.4775 28.1625 ;
|
||||
RECT 6.0525 27.9125 6.1175 28.1875 ;
|
||||
RECT 6.2425 27.9125 6.3075 28.1875 ;
|
||||
RECT 6.4125 27.9125 6.4775 28.1875 ;
|
||||
RECT 6.4125 27.0675 6.4775 27.2025 ;
|
||||
RECT 6.02 27.56 6.155 27.625 ;
|
||||
RECT 6.02 27.515 6.155 27.58 ;
|
||||
RECT 6.545 26.9325 7.295 26.9975 ;
|
||||
RECT 6.545 28.2775 7.295 28.3425 ;
|
||||
RECT 7.1625 28.0275 7.2275 28.31 ;
|
||||
|
|
@ -5250,40 +5250,40 @@ MACRO sram_2_16_1_freepdk45
|
|||
RECT 6.82 27.345 6.955 27.41 ;
|
||||
RECT 7.295 26.9325 7.855 26.9975 ;
|
||||
RECT 7.295 28.2775 7.855 28.3425 ;
|
||||
RECT 7.7225 28.0275 7.7875 28.2775 ;
|
||||
RECT 7.7225 27.9125 7.7875 28.2775 ;
|
||||
RECT 7.7225 26.9975 7.7875 27.1325 ;
|
||||
RECT 7.3625 26.9975 7.4275 27.0675 ;
|
||||
RECT 7.3625 28.1625 7.4275 28.2775 ;
|
||||
RECT 7.5525 27.1 7.6175 28.1625 ;
|
||||
RECT 7.295 27.56 7.33 27.625 ;
|
||||
RECT 7.6175 27.56 7.855 27.625 ;
|
||||
RECT 7.3625 28.1875 7.4275 28.2775 ;
|
||||
RECT 7.5525 27.1 7.6175 28.0475 ;
|
||||
RECT 7.295 27.515 7.33 27.58 ;
|
||||
RECT 7.6175 27.515 7.855 27.58 ;
|
||||
RECT 7.3625 27.2025 7.4275 27.3375 ;
|
||||
RECT 7.5525 27.2025 7.6175 27.3375 ;
|
||||
RECT 7.3625 28.0275 7.4275 28.1625 ;
|
||||
RECT 7.5525 28.0275 7.6175 28.1625 ;
|
||||
RECT 7.7225 28.0275 7.7875 28.1625 ;
|
||||
RECT 7.3625 27.9125 7.4275 28.1875 ;
|
||||
RECT 7.5525 27.9125 7.6175 28.1875 ;
|
||||
RECT 7.7225 27.9125 7.7875 28.1875 ;
|
||||
RECT 7.7225 27.0675 7.7875 27.2025 ;
|
||||
RECT 7.33 27.56 7.465 27.625 ;
|
||||
RECT 7.33 27.515 7.465 27.58 ;
|
||||
RECT 6.545 27.8775 6.68 27.9425 ;
|
||||
RECT 5.5325 27.875 5.5975 28.01 ;
|
||||
RECT 5.46 29.6225 5.595 29.6875 ;
|
||||
RECT 5.915 29.6225 6.05 29.6875 ;
|
||||
RECT 5.985 29.6225 6.545 29.6875 ;
|
||||
RECT 5.985 28.2775 6.545 28.3425 ;
|
||||
RECT 6.4125 28.3425 6.4775 28.5925 ;
|
||||
RECT 6.4125 28.3425 6.4775 28.7075 ;
|
||||
RECT 6.4125 29.4875 6.4775 29.6225 ;
|
||||
RECT 6.0525 29.5525 6.1175 29.6225 ;
|
||||
RECT 6.0525 28.3425 6.1175 28.4575 ;
|
||||
RECT 6.2425 28.4575 6.3075 29.52 ;
|
||||
RECT 5.985 28.995 6.02 29.06 ;
|
||||
RECT 6.3075 28.995 6.545 29.06 ;
|
||||
RECT 6.0525 28.3425 6.1175 28.4325 ;
|
||||
RECT 6.2425 28.5725 6.3075 29.52 ;
|
||||
RECT 5.985 29.04 6.02 29.105 ;
|
||||
RECT 6.3075 29.04 6.545 29.105 ;
|
||||
RECT 6.0525 29.3525 6.1175 29.4875 ;
|
||||
RECT 6.2425 29.3525 6.3075 29.4875 ;
|
||||
RECT 6.0525 28.7475 6.1175 28.8825 ;
|
||||
RECT 6.2425 28.7475 6.3075 28.8825 ;
|
||||
RECT 6.4125 28.5925 6.4775 28.7275 ;
|
||||
RECT 6.0525 28.8125 6.1175 29.0875 ;
|
||||
RECT 6.2425 28.8125 6.3075 29.0875 ;
|
||||
RECT 6.4125 28.7075 6.4775 28.9825 ;
|
||||
RECT 6.4125 29.5525 6.4775 29.6875 ;
|
||||
RECT 6.02 29.07 6.155 29.135 ;
|
||||
RECT 6.02 29.115 6.155 29.18 ;
|
||||
RECT 6.545 29.6225 7.295 29.6875 ;
|
||||
RECT 6.545 28.2775 7.295 28.3425 ;
|
||||
RECT 7.1625 28.31 7.2275 28.5925 ;
|
||||
|
|
@ -5313,40 +5313,40 @@ MACRO sram_2_16_1_freepdk45
|
|||
RECT 6.82 29.285 6.955 29.35 ;
|
||||
RECT 7.295 29.6225 7.855 29.6875 ;
|
||||
RECT 7.295 28.2775 7.855 28.3425 ;
|
||||
RECT 7.7225 28.3425 7.7875 28.5925 ;
|
||||
RECT 7.7225 28.3425 7.7875 28.7075 ;
|
||||
RECT 7.7225 29.4875 7.7875 29.6225 ;
|
||||
RECT 7.3625 29.5525 7.4275 29.6225 ;
|
||||
RECT 7.3625 28.3425 7.4275 28.4575 ;
|
||||
RECT 7.5525 28.4575 7.6175 29.52 ;
|
||||
RECT 7.295 28.995 7.33 29.06 ;
|
||||
RECT 7.6175 28.995 7.855 29.06 ;
|
||||
RECT 7.3625 28.3425 7.4275 28.4325 ;
|
||||
RECT 7.5525 28.5725 7.6175 29.52 ;
|
||||
RECT 7.295 29.04 7.33 29.105 ;
|
||||
RECT 7.6175 29.04 7.855 29.105 ;
|
||||
RECT 7.3625 29.3525 7.4275 29.4875 ;
|
||||
RECT 7.5525 29.3525 7.6175 29.4875 ;
|
||||
RECT 7.3625 28.7475 7.4275 28.8825 ;
|
||||
RECT 7.5525 28.7475 7.6175 28.8825 ;
|
||||
RECT 7.7225 28.5925 7.7875 28.7275 ;
|
||||
RECT 7.3625 28.8125 7.4275 29.0875 ;
|
||||
RECT 7.5525 28.8125 7.6175 29.0875 ;
|
||||
RECT 7.7225 28.7075 7.7875 28.9825 ;
|
||||
RECT 7.7225 29.5525 7.7875 29.6875 ;
|
||||
RECT 7.33 29.07 7.465 29.135 ;
|
||||
RECT 7.33 29.115 7.465 29.18 ;
|
||||
RECT 6.545 28.6775 6.68 28.7425 ;
|
||||
RECT 5.5325 28.61 5.5975 28.745 ;
|
||||
RECT 5.46 30.9675 5.595 31.0325 ;
|
||||
RECT 5.915 30.9675 6.05 31.0325 ;
|
||||
RECT 5.985 29.6225 6.545 29.6875 ;
|
||||
RECT 5.985 30.9675 6.545 31.0325 ;
|
||||
RECT 6.4125 30.7175 6.4775 30.9675 ;
|
||||
RECT 6.4125 30.6025 6.4775 30.9675 ;
|
||||
RECT 6.4125 29.6875 6.4775 29.8225 ;
|
||||
RECT 6.0525 29.6875 6.1175 29.7575 ;
|
||||
RECT 6.0525 30.8525 6.1175 30.9675 ;
|
||||
RECT 6.2425 29.79 6.3075 30.8525 ;
|
||||
RECT 5.985 30.25 6.02 30.315 ;
|
||||
RECT 6.3075 30.25 6.545 30.315 ;
|
||||
RECT 6.0525 30.8775 6.1175 30.9675 ;
|
||||
RECT 6.2425 29.79 6.3075 30.7375 ;
|
||||
RECT 5.985 30.205 6.02 30.27 ;
|
||||
RECT 6.3075 30.205 6.545 30.27 ;
|
||||
RECT 6.0525 29.8925 6.1175 30.0275 ;
|
||||
RECT 6.2425 29.8925 6.3075 30.0275 ;
|
||||
RECT 6.0525 30.7175 6.1175 30.8525 ;
|
||||
RECT 6.2425 30.7175 6.3075 30.8525 ;
|
||||
RECT 6.4125 30.7175 6.4775 30.8525 ;
|
||||
RECT 6.0525 30.6025 6.1175 30.8775 ;
|
||||
RECT 6.2425 30.6025 6.3075 30.8775 ;
|
||||
RECT 6.4125 30.6025 6.4775 30.8775 ;
|
||||
RECT 6.4125 29.7575 6.4775 29.8925 ;
|
||||
RECT 6.02 30.25 6.155 30.315 ;
|
||||
RECT 6.02 30.205 6.155 30.27 ;
|
||||
RECT 6.545 29.6225 7.295 29.6875 ;
|
||||
RECT 6.545 30.9675 7.295 31.0325 ;
|
||||
RECT 7.1625 30.7175 7.2275 31.0 ;
|
||||
|
|
@ -5376,40 +5376,40 @@ MACRO sram_2_16_1_freepdk45
|
|||
RECT 6.82 30.035 6.955 30.1 ;
|
||||
RECT 7.295 29.6225 7.855 29.6875 ;
|
||||
RECT 7.295 30.9675 7.855 31.0325 ;
|
||||
RECT 7.7225 30.7175 7.7875 30.9675 ;
|
||||
RECT 7.7225 30.6025 7.7875 30.9675 ;
|
||||
RECT 7.7225 29.6875 7.7875 29.8225 ;
|
||||
RECT 7.3625 29.6875 7.4275 29.7575 ;
|
||||
RECT 7.3625 30.8525 7.4275 30.9675 ;
|
||||
RECT 7.5525 29.79 7.6175 30.8525 ;
|
||||
RECT 7.295 30.25 7.33 30.315 ;
|
||||
RECT 7.6175 30.25 7.855 30.315 ;
|
||||
RECT 7.3625 30.8775 7.4275 30.9675 ;
|
||||
RECT 7.5525 29.79 7.6175 30.7375 ;
|
||||
RECT 7.295 30.205 7.33 30.27 ;
|
||||
RECT 7.6175 30.205 7.855 30.27 ;
|
||||
RECT 7.3625 29.8925 7.4275 30.0275 ;
|
||||
RECT 7.5525 29.8925 7.6175 30.0275 ;
|
||||
RECT 7.3625 30.7175 7.4275 30.8525 ;
|
||||
RECT 7.5525 30.7175 7.6175 30.8525 ;
|
||||
RECT 7.7225 30.7175 7.7875 30.8525 ;
|
||||
RECT 7.3625 30.6025 7.4275 30.8775 ;
|
||||
RECT 7.5525 30.6025 7.6175 30.8775 ;
|
||||
RECT 7.7225 30.6025 7.7875 30.8775 ;
|
||||
RECT 7.7225 29.7575 7.7875 29.8925 ;
|
||||
RECT 7.33 30.25 7.465 30.315 ;
|
||||
RECT 7.33 30.205 7.465 30.27 ;
|
||||
RECT 6.545 30.5675 6.68 30.6325 ;
|
||||
RECT 5.5325 30.565 5.5975 30.7 ;
|
||||
RECT 5.46 32.3125 5.595 32.3775 ;
|
||||
RECT 5.915 32.3125 6.05 32.3775 ;
|
||||
RECT 5.985 32.3125 6.545 32.3775 ;
|
||||
RECT 5.985 30.9675 6.545 31.0325 ;
|
||||
RECT 6.4125 31.0325 6.4775 31.2825 ;
|
||||
RECT 6.4125 31.0325 6.4775 31.3975 ;
|
||||
RECT 6.4125 32.1775 6.4775 32.3125 ;
|
||||
RECT 6.0525 32.2425 6.1175 32.3125 ;
|
||||
RECT 6.0525 31.0325 6.1175 31.1475 ;
|
||||
RECT 6.2425 31.1475 6.3075 32.21 ;
|
||||
RECT 5.985 31.685 6.02 31.75 ;
|
||||
RECT 6.3075 31.685 6.545 31.75 ;
|
||||
RECT 6.0525 31.0325 6.1175 31.1225 ;
|
||||
RECT 6.2425 31.2625 6.3075 32.21 ;
|
||||
RECT 5.985 31.73 6.02 31.795 ;
|
||||
RECT 6.3075 31.73 6.545 31.795 ;
|
||||
RECT 6.0525 32.0425 6.1175 32.1775 ;
|
||||
RECT 6.2425 32.0425 6.3075 32.1775 ;
|
||||
RECT 6.0525 31.4375 6.1175 31.5725 ;
|
||||
RECT 6.2425 31.4375 6.3075 31.5725 ;
|
||||
RECT 6.4125 31.2825 6.4775 31.4175 ;
|
||||
RECT 6.0525 31.5025 6.1175 31.7775 ;
|
||||
RECT 6.2425 31.5025 6.3075 31.7775 ;
|
||||
RECT 6.4125 31.3975 6.4775 31.6725 ;
|
||||
RECT 6.4125 32.2425 6.4775 32.3775 ;
|
||||
RECT 6.02 31.76 6.155 31.825 ;
|
||||
RECT 6.02 31.805 6.155 31.87 ;
|
||||
RECT 6.545 32.3125 7.295 32.3775 ;
|
||||
RECT 6.545 30.9675 7.295 31.0325 ;
|
||||
RECT 7.1625 31.0 7.2275 31.2825 ;
|
||||
|
|
@ -5439,40 +5439,40 @@ MACRO sram_2_16_1_freepdk45
|
|||
RECT 6.82 31.975 6.955 32.04 ;
|
||||
RECT 7.295 32.3125 7.855 32.3775 ;
|
||||
RECT 7.295 30.9675 7.855 31.0325 ;
|
||||
RECT 7.7225 31.0325 7.7875 31.2825 ;
|
||||
RECT 7.7225 31.0325 7.7875 31.3975 ;
|
||||
RECT 7.7225 32.1775 7.7875 32.3125 ;
|
||||
RECT 7.3625 32.2425 7.4275 32.3125 ;
|
||||
RECT 7.3625 31.0325 7.4275 31.1475 ;
|
||||
RECT 7.5525 31.1475 7.6175 32.21 ;
|
||||
RECT 7.295 31.685 7.33 31.75 ;
|
||||
RECT 7.6175 31.685 7.855 31.75 ;
|
||||
RECT 7.3625 31.0325 7.4275 31.1225 ;
|
||||
RECT 7.5525 31.2625 7.6175 32.21 ;
|
||||
RECT 7.295 31.73 7.33 31.795 ;
|
||||
RECT 7.6175 31.73 7.855 31.795 ;
|
||||
RECT 7.3625 32.0425 7.4275 32.1775 ;
|
||||
RECT 7.5525 32.0425 7.6175 32.1775 ;
|
||||
RECT 7.3625 31.4375 7.4275 31.5725 ;
|
||||
RECT 7.5525 31.4375 7.6175 31.5725 ;
|
||||
RECT 7.7225 31.2825 7.7875 31.4175 ;
|
||||
RECT 7.3625 31.5025 7.4275 31.7775 ;
|
||||
RECT 7.5525 31.5025 7.6175 31.7775 ;
|
||||
RECT 7.7225 31.3975 7.7875 31.6725 ;
|
||||
RECT 7.7225 32.2425 7.7875 32.3775 ;
|
||||
RECT 7.33 31.76 7.465 31.825 ;
|
||||
RECT 7.33 31.805 7.465 31.87 ;
|
||||
RECT 6.545 31.3675 6.68 31.4325 ;
|
||||
RECT 5.5325 31.3 5.5975 31.435 ;
|
||||
RECT 5.46 33.6575 5.595 33.7225 ;
|
||||
RECT 5.915 33.6575 6.05 33.7225 ;
|
||||
RECT 5.985 32.3125 6.545 32.3775 ;
|
||||
RECT 5.985 33.6575 6.545 33.7225 ;
|
||||
RECT 6.4125 33.4075 6.4775 33.6575 ;
|
||||
RECT 6.4125 33.2925 6.4775 33.6575 ;
|
||||
RECT 6.4125 32.3775 6.4775 32.5125 ;
|
||||
RECT 6.0525 32.3775 6.1175 32.4475 ;
|
||||
RECT 6.0525 33.5425 6.1175 33.6575 ;
|
||||
RECT 6.2425 32.48 6.3075 33.5425 ;
|
||||
RECT 5.985 32.94 6.02 33.005 ;
|
||||
RECT 6.3075 32.94 6.545 33.005 ;
|
||||
RECT 6.0525 33.5675 6.1175 33.6575 ;
|
||||
RECT 6.2425 32.48 6.3075 33.4275 ;
|
||||
RECT 5.985 32.895 6.02 32.96 ;
|
||||
RECT 6.3075 32.895 6.545 32.96 ;
|
||||
RECT 6.0525 32.5825 6.1175 32.7175 ;
|
||||
RECT 6.2425 32.5825 6.3075 32.7175 ;
|
||||
RECT 6.0525 33.4075 6.1175 33.5425 ;
|
||||
RECT 6.2425 33.4075 6.3075 33.5425 ;
|
||||
RECT 6.4125 33.4075 6.4775 33.5425 ;
|
||||
RECT 6.0525 33.2925 6.1175 33.5675 ;
|
||||
RECT 6.2425 33.2925 6.3075 33.5675 ;
|
||||
RECT 6.4125 33.2925 6.4775 33.5675 ;
|
||||
RECT 6.4125 32.4475 6.4775 32.5825 ;
|
||||
RECT 6.02 32.94 6.155 33.005 ;
|
||||
RECT 6.02 32.895 6.155 32.96 ;
|
||||
RECT 6.545 32.3125 7.295 32.3775 ;
|
||||
RECT 6.545 33.6575 7.295 33.7225 ;
|
||||
RECT 7.1625 33.4075 7.2275 33.69 ;
|
||||
|
|
@ -5502,40 +5502,40 @@ MACRO sram_2_16_1_freepdk45
|
|||
RECT 6.82 32.725 6.955 32.79 ;
|
||||
RECT 7.295 32.3125 7.855 32.3775 ;
|
||||
RECT 7.295 33.6575 7.855 33.7225 ;
|
||||
RECT 7.7225 33.4075 7.7875 33.6575 ;
|
||||
RECT 7.7225 33.2925 7.7875 33.6575 ;
|
||||
RECT 7.7225 32.3775 7.7875 32.5125 ;
|
||||
RECT 7.3625 32.3775 7.4275 32.4475 ;
|
||||
RECT 7.3625 33.5425 7.4275 33.6575 ;
|
||||
RECT 7.5525 32.48 7.6175 33.5425 ;
|
||||
RECT 7.295 32.94 7.33 33.005 ;
|
||||
RECT 7.6175 32.94 7.855 33.005 ;
|
||||
RECT 7.3625 33.5675 7.4275 33.6575 ;
|
||||
RECT 7.5525 32.48 7.6175 33.4275 ;
|
||||
RECT 7.295 32.895 7.33 32.96 ;
|
||||
RECT 7.6175 32.895 7.855 32.96 ;
|
||||
RECT 7.3625 32.5825 7.4275 32.7175 ;
|
||||
RECT 7.5525 32.5825 7.6175 32.7175 ;
|
||||
RECT 7.3625 33.4075 7.4275 33.5425 ;
|
||||
RECT 7.5525 33.4075 7.6175 33.5425 ;
|
||||
RECT 7.7225 33.4075 7.7875 33.5425 ;
|
||||
RECT 7.3625 33.2925 7.4275 33.5675 ;
|
||||
RECT 7.5525 33.2925 7.6175 33.5675 ;
|
||||
RECT 7.7225 33.2925 7.7875 33.5675 ;
|
||||
RECT 7.7225 32.4475 7.7875 32.5825 ;
|
||||
RECT 7.33 32.94 7.465 33.005 ;
|
||||
RECT 7.33 32.895 7.465 32.96 ;
|
||||
RECT 6.545 33.2575 6.68 33.3225 ;
|
||||
RECT 5.5325 33.255 5.5975 33.39 ;
|
||||
RECT 5.46 35.0025 5.595 35.0675 ;
|
||||
RECT 5.915 35.0025 6.05 35.0675 ;
|
||||
RECT 5.985 35.0025 6.545 35.0675 ;
|
||||
RECT 5.985 33.6575 6.545 33.7225 ;
|
||||
RECT 6.4125 33.7225 6.4775 33.9725 ;
|
||||
RECT 6.4125 33.7225 6.4775 34.0875 ;
|
||||
RECT 6.4125 34.8675 6.4775 35.0025 ;
|
||||
RECT 6.0525 34.9325 6.1175 35.0025 ;
|
||||
RECT 6.0525 33.7225 6.1175 33.8375 ;
|
||||
RECT 6.2425 33.8375 6.3075 34.9 ;
|
||||
RECT 5.985 34.375 6.02 34.44 ;
|
||||
RECT 6.3075 34.375 6.545 34.44 ;
|
||||
RECT 6.0525 33.7225 6.1175 33.8125 ;
|
||||
RECT 6.2425 33.9525 6.3075 34.9 ;
|
||||
RECT 5.985 34.42 6.02 34.485 ;
|
||||
RECT 6.3075 34.42 6.545 34.485 ;
|
||||
RECT 6.0525 34.7325 6.1175 34.8675 ;
|
||||
RECT 6.2425 34.7325 6.3075 34.8675 ;
|
||||
RECT 6.0525 34.1275 6.1175 34.2625 ;
|
||||
RECT 6.2425 34.1275 6.3075 34.2625 ;
|
||||
RECT 6.4125 33.9725 6.4775 34.1075 ;
|
||||
RECT 6.0525 34.1925 6.1175 34.4675 ;
|
||||
RECT 6.2425 34.1925 6.3075 34.4675 ;
|
||||
RECT 6.4125 34.0875 6.4775 34.3625 ;
|
||||
RECT 6.4125 34.9325 6.4775 35.0675 ;
|
||||
RECT 6.02 34.45 6.155 34.515 ;
|
||||
RECT 6.02 34.495 6.155 34.56 ;
|
||||
RECT 6.545 35.0025 7.295 35.0675 ;
|
||||
RECT 6.545 33.6575 7.295 33.7225 ;
|
||||
RECT 7.1625 33.69 7.2275 33.9725 ;
|
||||
|
|
@ -5565,40 +5565,40 @@ MACRO sram_2_16_1_freepdk45
|
|||
RECT 6.82 34.665 6.955 34.73 ;
|
||||
RECT 7.295 35.0025 7.855 35.0675 ;
|
||||
RECT 7.295 33.6575 7.855 33.7225 ;
|
||||
RECT 7.7225 33.7225 7.7875 33.9725 ;
|
||||
RECT 7.7225 33.7225 7.7875 34.0875 ;
|
||||
RECT 7.7225 34.8675 7.7875 35.0025 ;
|
||||
RECT 7.3625 34.9325 7.4275 35.0025 ;
|
||||
RECT 7.3625 33.7225 7.4275 33.8375 ;
|
||||
RECT 7.5525 33.8375 7.6175 34.9 ;
|
||||
RECT 7.295 34.375 7.33 34.44 ;
|
||||
RECT 7.6175 34.375 7.855 34.44 ;
|
||||
RECT 7.3625 33.7225 7.4275 33.8125 ;
|
||||
RECT 7.5525 33.9525 7.6175 34.9 ;
|
||||
RECT 7.295 34.42 7.33 34.485 ;
|
||||
RECT 7.6175 34.42 7.855 34.485 ;
|
||||
RECT 7.3625 34.7325 7.4275 34.8675 ;
|
||||
RECT 7.5525 34.7325 7.6175 34.8675 ;
|
||||
RECT 7.3625 34.1275 7.4275 34.2625 ;
|
||||
RECT 7.5525 34.1275 7.6175 34.2625 ;
|
||||
RECT 7.7225 33.9725 7.7875 34.1075 ;
|
||||
RECT 7.3625 34.1925 7.4275 34.4675 ;
|
||||
RECT 7.5525 34.1925 7.6175 34.4675 ;
|
||||
RECT 7.7225 34.0875 7.7875 34.3625 ;
|
||||
RECT 7.7225 34.9325 7.7875 35.0675 ;
|
||||
RECT 7.33 34.45 7.465 34.515 ;
|
||||
RECT 7.33 34.495 7.465 34.56 ;
|
||||
RECT 6.545 34.0575 6.68 34.1225 ;
|
||||
RECT 5.5325 33.99 5.5975 34.125 ;
|
||||
RECT 5.46 36.3475 5.595 36.4125 ;
|
||||
RECT 5.915 36.3475 6.05 36.4125 ;
|
||||
RECT 5.985 35.0025 6.545 35.0675 ;
|
||||
RECT 5.985 36.3475 6.545 36.4125 ;
|
||||
RECT 6.4125 36.0975 6.4775 36.3475 ;
|
||||
RECT 6.4125 35.9825 6.4775 36.3475 ;
|
||||
RECT 6.4125 35.0675 6.4775 35.2025 ;
|
||||
RECT 6.0525 35.0675 6.1175 35.1375 ;
|
||||
RECT 6.0525 36.2325 6.1175 36.3475 ;
|
||||
RECT 6.2425 35.17 6.3075 36.2325 ;
|
||||
RECT 5.985 35.63 6.02 35.695 ;
|
||||
RECT 6.3075 35.63 6.545 35.695 ;
|
||||
RECT 6.0525 36.2575 6.1175 36.3475 ;
|
||||
RECT 6.2425 35.17 6.3075 36.1175 ;
|
||||
RECT 5.985 35.585 6.02 35.65 ;
|
||||
RECT 6.3075 35.585 6.545 35.65 ;
|
||||
RECT 6.0525 35.2725 6.1175 35.4075 ;
|
||||
RECT 6.2425 35.2725 6.3075 35.4075 ;
|
||||
RECT 6.0525 36.0975 6.1175 36.2325 ;
|
||||
RECT 6.2425 36.0975 6.3075 36.2325 ;
|
||||
RECT 6.4125 36.0975 6.4775 36.2325 ;
|
||||
RECT 6.0525 35.9825 6.1175 36.2575 ;
|
||||
RECT 6.2425 35.9825 6.3075 36.2575 ;
|
||||
RECT 6.4125 35.9825 6.4775 36.2575 ;
|
||||
RECT 6.4125 35.1375 6.4775 35.2725 ;
|
||||
RECT 6.02 35.63 6.155 35.695 ;
|
||||
RECT 6.02 35.585 6.155 35.65 ;
|
||||
RECT 6.545 35.0025 7.295 35.0675 ;
|
||||
RECT 6.545 36.3475 7.295 36.4125 ;
|
||||
RECT 7.1625 36.0975 7.2275 36.38 ;
|
||||
|
|
@ -5628,40 +5628,40 @@ MACRO sram_2_16_1_freepdk45
|
|||
RECT 6.82 35.415 6.955 35.48 ;
|
||||
RECT 7.295 35.0025 7.855 35.0675 ;
|
||||
RECT 7.295 36.3475 7.855 36.4125 ;
|
||||
RECT 7.7225 36.0975 7.7875 36.3475 ;
|
||||
RECT 7.7225 35.9825 7.7875 36.3475 ;
|
||||
RECT 7.7225 35.0675 7.7875 35.2025 ;
|
||||
RECT 7.3625 35.0675 7.4275 35.1375 ;
|
||||
RECT 7.3625 36.2325 7.4275 36.3475 ;
|
||||
RECT 7.5525 35.17 7.6175 36.2325 ;
|
||||
RECT 7.295 35.63 7.33 35.695 ;
|
||||
RECT 7.6175 35.63 7.855 35.695 ;
|
||||
RECT 7.3625 36.2575 7.4275 36.3475 ;
|
||||
RECT 7.5525 35.17 7.6175 36.1175 ;
|
||||
RECT 7.295 35.585 7.33 35.65 ;
|
||||
RECT 7.6175 35.585 7.855 35.65 ;
|
||||
RECT 7.3625 35.2725 7.4275 35.4075 ;
|
||||
RECT 7.5525 35.2725 7.6175 35.4075 ;
|
||||
RECT 7.3625 36.0975 7.4275 36.2325 ;
|
||||
RECT 7.5525 36.0975 7.6175 36.2325 ;
|
||||
RECT 7.7225 36.0975 7.7875 36.2325 ;
|
||||
RECT 7.3625 35.9825 7.4275 36.2575 ;
|
||||
RECT 7.5525 35.9825 7.6175 36.2575 ;
|
||||
RECT 7.7225 35.9825 7.7875 36.2575 ;
|
||||
RECT 7.7225 35.1375 7.7875 35.2725 ;
|
||||
RECT 7.33 35.63 7.465 35.695 ;
|
||||
RECT 7.33 35.585 7.465 35.65 ;
|
||||
RECT 6.545 35.9475 6.68 36.0125 ;
|
||||
RECT 5.5325 35.945 5.5975 36.08 ;
|
||||
RECT 5.46 37.6925 5.595 37.7575 ;
|
||||
RECT 5.915 37.6925 6.05 37.7575 ;
|
||||
RECT 5.985 37.6925 6.545 37.7575 ;
|
||||
RECT 5.985 36.3475 6.545 36.4125 ;
|
||||
RECT 6.4125 36.4125 6.4775 36.6625 ;
|
||||
RECT 6.4125 36.4125 6.4775 36.7775 ;
|
||||
RECT 6.4125 37.5575 6.4775 37.6925 ;
|
||||
RECT 6.0525 37.6225 6.1175 37.6925 ;
|
||||
RECT 6.0525 36.4125 6.1175 36.5275 ;
|
||||
RECT 6.2425 36.5275 6.3075 37.59 ;
|
||||
RECT 5.985 37.065 6.02 37.13 ;
|
||||
RECT 6.3075 37.065 6.545 37.13 ;
|
||||
RECT 6.0525 36.4125 6.1175 36.5025 ;
|
||||
RECT 6.2425 36.6425 6.3075 37.59 ;
|
||||
RECT 5.985 37.11 6.02 37.175 ;
|
||||
RECT 6.3075 37.11 6.545 37.175 ;
|
||||
RECT 6.0525 37.4225 6.1175 37.5575 ;
|
||||
RECT 6.2425 37.4225 6.3075 37.5575 ;
|
||||
RECT 6.0525 36.8175 6.1175 36.9525 ;
|
||||
RECT 6.2425 36.8175 6.3075 36.9525 ;
|
||||
RECT 6.4125 36.6625 6.4775 36.7975 ;
|
||||
RECT 6.0525 36.8825 6.1175 37.1575 ;
|
||||
RECT 6.2425 36.8825 6.3075 37.1575 ;
|
||||
RECT 6.4125 36.7775 6.4775 37.0525 ;
|
||||
RECT 6.4125 37.6225 6.4775 37.7575 ;
|
||||
RECT 6.02 37.14 6.155 37.205 ;
|
||||
RECT 6.02 37.185 6.155 37.25 ;
|
||||
RECT 6.545 37.6925 7.295 37.7575 ;
|
||||
RECT 6.545 36.3475 7.295 36.4125 ;
|
||||
RECT 7.1625 36.38 7.2275 36.6625 ;
|
||||
|
|
@ -5691,40 +5691,40 @@ MACRO sram_2_16_1_freepdk45
|
|||
RECT 6.82 37.355 6.955 37.42 ;
|
||||
RECT 7.295 37.6925 7.855 37.7575 ;
|
||||
RECT 7.295 36.3475 7.855 36.4125 ;
|
||||
RECT 7.7225 36.4125 7.7875 36.6625 ;
|
||||
RECT 7.7225 36.4125 7.7875 36.7775 ;
|
||||
RECT 7.7225 37.5575 7.7875 37.6925 ;
|
||||
RECT 7.3625 37.6225 7.4275 37.6925 ;
|
||||
RECT 7.3625 36.4125 7.4275 36.5275 ;
|
||||
RECT 7.5525 36.5275 7.6175 37.59 ;
|
||||
RECT 7.295 37.065 7.33 37.13 ;
|
||||
RECT 7.6175 37.065 7.855 37.13 ;
|
||||
RECT 7.3625 36.4125 7.4275 36.5025 ;
|
||||
RECT 7.5525 36.6425 7.6175 37.59 ;
|
||||
RECT 7.295 37.11 7.33 37.175 ;
|
||||
RECT 7.6175 37.11 7.855 37.175 ;
|
||||
RECT 7.3625 37.4225 7.4275 37.5575 ;
|
||||
RECT 7.5525 37.4225 7.6175 37.5575 ;
|
||||
RECT 7.3625 36.8175 7.4275 36.9525 ;
|
||||
RECT 7.5525 36.8175 7.6175 36.9525 ;
|
||||
RECT 7.7225 36.6625 7.7875 36.7975 ;
|
||||
RECT 7.3625 36.8825 7.4275 37.1575 ;
|
||||
RECT 7.5525 36.8825 7.6175 37.1575 ;
|
||||
RECT 7.7225 36.7775 7.7875 37.0525 ;
|
||||
RECT 7.7225 37.6225 7.7875 37.7575 ;
|
||||
RECT 7.33 37.14 7.465 37.205 ;
|
||||
RECT 7.33 37.185 7.465 37.25 ;
|
||||
RECT 6.545 36.7475 6.68 36.8125 ;
|
||||
RECT 5.5325 36.68 5.5975 36.815 ;
|
||||
RECT 5.46 39.0375 5.595 39.1025 ;
|
||||
RECT 5.915 39.0375 6.05 39.1025 ;
|
||||
RECT 5.985 37.6925 6.545 37.7575 ;
|
||||
RECT 5.985 39.0375 6.545 39.1025 ;
|
||||
RECT 6.4125 38.7875 6.4775 39.0375 ;
|
||||
RECT 6.4125 38.6725 6.4775 39.0375 ;
|
||||
RECT 6.4125 37.7575 6.4775 37.8925 ;
|
||||
RECT 6.0525 37.7575 6.1175 37.8275 ;
|
||||
RECT 6.0525 38.9225 6.1175 39.0375 ;
|
||||
RECT 6.2425 37.86 6.3075 38.9225 ;
|
||||
RECT 5.985 38.32 6.02 38.385 ;
|
||||
RECT 6.3075 38.32 6.545 38.385 ;
|
||||
RECT 6.0525 38.9475 6.1175 39.0375 ;
|
||||
RECT 6.2425 37.86 6.3075 38.8075 ;
|
||||
RECT 5.985 38.275 6.02 38.34 ;
|
||||
RECT 6.3075 38.275 6.545 38.34 ;
|
||||
RECT 6.0525 37.9625 6.1175 38.0975 ;
|
||||
RECT 6.2425 37.9625 6.3075 38.0975 ;
|
||||
RECT 6.0525 38.7875 6.1175 38.9225 ;
|
||||
RECT 6.2425 38.7875 6.3075 38.9225 ;
|
||||
RECT 6.4125 38.7875 6.4775 38.9225 ;
|
||||
RECT 6.0525 38.6725 6.1175 38.9475 ;
|
||||
RECT 6.2425 38.6725 6.3075 38.9475 ;
|
||||
RECT 6.4125 38.6725 6.4775 38.9475 ;
|
||||
RECT 6.4125 37.8275 6.4775 37.9625 ;
|
||||
RECT 6.02 38.32 6.155 38.385 ;
|
||||
RECT 6.02 38.275 6.155 38.34 ;
|
||||
RECT 6.545 37.6925 7.295 37.7575 ;
|
||||
RECT 6.545 39.0375 7.295 39.1025 ;
|
||||
RECT 7.1625 38.7875 7.2275 39.07 ;
|
||||
|
|
@ -5754,40 +5754,40 @@ MACRO sram_2_16_1_freepdk45
|
|||
RECT 6.82 38.105 6.955 38.17 ;
|
||||
RECT 7.295 37.6925 7.855 37.7575 ;
|
||||
RECT 7.295 39.0375 7.855 39.1025 ;
|
||||
RECT 7.7225 38.7875 7.7875 39.0375 ;
|
||||
RECT 7.7225 38.6725 7.7875 39.0375 ;
|
||||
RECT 7.7225 37.7575 7.7875 37.8925 ;
|
||||
RECT 7.3625 37.7575 7.4275 37.8275 ;
|
||||
RECT 7.3625 38.9225 7.4275 39.0375 ;
|
||||
RECT 7.5525 37.86 7.6175 38.9225 ;
|
||||
RECT 7.295 38.32 7.33 38.385 ;
|
||||
RECT 7.6175 38.32 7.855 38.385 ;
|
||||
RECT 7.3625 38.9475 7.4275 39.0375 ;
|
||||
RECT 7.5525 37.86 7.6175 38.8075 ;
|
||||
RECT 7.295 38.275 7.33 38.34 ;
|
||||
RECT 7.6175 38.275 7.855 38.34 ;
|
||||
RECT 7.3625 37.9625 7.4275 38.0975 ;
|
||||
RECT 7.5525 37.9625 7.6175 38.0975 ;
|
||||
RECT 7.3625 38.7875 7.4275 38.9225 ;
|
||||
RECT 7.5525 38.7875 7.6175 38.9225 ;
|
||||
RECT 7.7225 38.7875 7.7875 38.9225 ;
|
||||
RECT 7.3625 38.6725 7.4275 38.9475 ;
|
||||
RECT 7.5525 38.6725 7.6175 38.9475 ;
|
||||
RECT 7.7225 38.6725 7.7875 38.9475 ;
|
||||
RECT 7.7225 37.8275 7.7875 37.9625 ;
|
||||
RECT 7.33 38.32 7.465 38.385 ;
|
||||
RECT 7.33 38.275 7.465 38.34 ;
|
||||
RECT 6.545 38.6375 6.68 38.7025 ;
|
||||
RECT 5.5325 38.635 5.5975 38.77 ;
|
||||
RECT 5.46 40.3825 5.595 40.4475 ;
|
||||
RECT 5.915 40.3825 6.05 40.4475 ;
|
||||
RECT 5.985 40.3825 6.545 40.4475 ;
|
||||
RECT 5.985 39.0375 6.545 39.1025 ;
|
||||
RECT 6.4125 39.1025 6.4775 39.3525 ;
|
||||
RECT 6.4125 39.1025 6.4775 39.4675 ;
|
||||
RECT 6.4125 40.2475 6.4775 40.3825 ;
|
||||
RECT 6.0525 40.3125 6.1175 40.3825 ;
|
||||
RECT 6.0525 39.1025 6.1175 39.2175 ;
|
||||
RECT 6.2425 39.2175 6.3075 40.28 ;
|
||||
RECT 5.985 39.755 6.02 39.82 ;
|
||||
RECT 6.3075 39.755 6.545 39.82 ;
|
||||
RECT 6.0525 39.1025 6.1175 39.1925 ;
|
||||
RECT 6.2425 39.3325 6.3075 40.28 ;
|
||||
RECT 5.985 39.8 6.02 39.865 ;
|
||||
RECT 6.3075 39.8 6.545 39.865 ;
|
||||
RECT 6.0525 40.1125 6.1175 40.2475 ;
|
||||
RECT 6.2425 40.1125 6.3075 40.2475 ;
|
||||
RECT 6.0525 39.5075 6.1175 39.6425 ;
|
||||
RECT 6.2425 39.5075 6.3075 39.6425 ;
|
||||
RECT 6.4125 39.3525 6.4775 39.4875 ;
|
||||
RECT 6.0525 39.5725 6.1175 39.8475 ;
|
||||
RECT 6.2425 39.5725 6.3075 39.8475 ;
|
||||
RECT 6.4125 39.4675 6.4775 39.7425 ;
|
||||
RECT 6.4125 40.3125 6.4775 40.4475 ;
|
||||
RECT 6.02 39.83 6.155 39.895 ;
|
||||
RECT 6.02 39.875 6.155 39.94 ;
|
||||
RECT 6.545 40.3825 7.295 40.4475 ;
|
||||
RECT 6.545 39.0375 7.295 39.1025 ;
|
||||
RECT 7.1625 39.07 7.2275 39.3525 ;
|
||||
|
|
@ -5817,20 +5817,20 @@ MACRO sram_2_16_1_freepdk45
|
|||
RECT 6.82 40.045 6.955 40.11 ;
|
||||
RECT 7.295 40.3825 7.855 40.4475 ;
|
||||
RECT 7.295 39.0375 7.855 39.1025 ;
|
||||
RECT 7.7225 39.1025 7.7875 39.3525 ;
|
||||
RECT 7.7225 39.1025 7.7875 39.4675 ;
|
||||
RECT 7.7225 40.2475 7.7875 40.3825 ;
|
||||
RECT 7.3625 40.3125 7.4275 40.3825 ;
|
||||
RECT 7.3625 39.1025 7.4275 39.2175 ;
|
||||
RECT 7.5525 39.2175 7.6175 40.28 ;
|
||||
RECT 7.295 39.755 7.33 39.82 ;
|
||||
RECT 7.6175 39.755 7.855 39.82 ;
|
||||
RECT 7.3625 39.1025 7.4275 39.1925 ;
|
||||
RECT 7.5525 39.3325 7.6175 40.28 ;
|
||||
RECT 7.295 39.8 7.33 39.865 ;
|
||||
RECT 7.6175 39.8 7.855 39.865 ;
|
||||
RECT 7.3625 40.1125 7.4275 40.2475 ;
|
||||
RECT 7.5525 40.1125 7.6175 40.2475 ;
|
||||
RECT 7.3625 39.5075 7.4275 39.6425 ;
|
||||
RECT 7.5525 39.5075 7.6175 39.6425 ;
|
||||
RECT 7.7225 39.3525 7.7875 39.4875 ;
|
||||
RECT 7.3625 39.5725 7.4275 39.8475 ;
|
||||
RECT 7.5525 39.5725 7.6175 39.8475 ;
|
||||
RECT 7.7225 39.4675 7.7875 39.7425 ;
|
||||
RECT 7.7225 40.3125 7.7875 40.4475 ;
|
||||
RECT 7.33 39.83 7.465 39.895 ;
|
||||
RECT 7.33 39.875 7.465 39.94 ;
|
||||
RECT 6.545 39.4375 6.68 39.5025 ;
|
||||
RECT 5.5325 39.37 5.5975 39.505 ;
|
||||
RECT 1.0825 5.02 1.1475 7.84 ;
|
||||
|
|
|
|||
|
|
@ -96,7 +96,8 @@ def isdiff(file1,file2):
|
|||
f2 = open(file2,"r")
|
||||
s2 = f2.readlines()
|
||||
for line in difflib.unified_diff(s1, s2):
|
||||
debug.error(line)
|
||||
debug.info(3,line)
|
||||
debug.error("MISMATCH {0} {1}".format(file1,file2))
|
||||
else:
|
||||
debug.info(2,"MATCH {0} {1}".format(file1,file2))
|
||||
return (check)
|
||||
|
|
|
|||
|
|
@ -13,11 +13,11 @@ class wire(path):
|
|||
The points are the center of the wire.
|
||||
The layer stack is the vertical, contact/via, and horizontal layers, respectively.
|
||||
"""
|
||||
unique_wire_id = 1
|
||||
unique_id = 1
|
||||
|
||||
def __init__(self, layer_stack, position_list):
|
||||
name = "wire_{0}".format(wire.unique_wire_id)
|
||||
wire.unique_wire_id += 1
|
||||
name = "wire_{0}".format(wire.unique_id)
|
||||
wire.unique_id += 1
|
||||
design.design.__init__(self, name)
|
||||
debug.info(3, "create wire obj {0}".format(name))
|
||||
|
||||
|
|
|
|||
|
|
@ -40,13 +40,11 @@ class wordline_driver(design.design):
|
|||
self.create_layout()
|
||||
|
||||
def add_layout(self):
|
||||
self.inv = pinv(name="pinverter",
|
||||
nmos_width=drc["minwidth_tx"],
|
||||
self.inv = pinv(nmos_width=drc["minwidth_tx"],
|
||||
beta=parameter["pinv_beta"])
|
||||
self.add_mod(self.inv)
|
||||
|
||||
self.NAND2 = nand_2(name="pnand2",
|
||||
nmos_width=2*drc["minwidth_tx"])
|
||||
self.NAND2 = nand_2(nmos_width=2*drc["minwidth_tx"])
|
||||
self.add_mod(self.NAND2)
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue