mirror of https://github.com/VLSIDA/OpenRAM.git
Skip pbitcell tests for now
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parent
ac8a16ebdf
commit
8752d799b4
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@ -13,9 +13,7 @@ import debug
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OPTS = globals.OPTS
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#@unittest.skip("SKIPPING 04_pbitcell_test")
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@unittest.skip("SKIPPING 04_pbitcell_test")
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class pbitcell_test(openram_test):
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def runTest(self):
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@ -11,7 +11,7 @@ import globals
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from globals import OPTS
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import debug
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#@unittest.skip("SKIPPING 05_pbitcell_array_test")
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@unittest.skip("SKIPPING 05_pbitcell_array_test")
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class pbitcell_array_test(openram_test):
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def runTest(self):
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@ -11,8 +11,8 @@ import globals
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from globals import OPTS
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import debug
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@unittest.skip("Multiported Bank not working yet")
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class single_bank_test(openram_test):
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@unittest.skip("SKIPPING 19_psingle_bank_test")
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class psingle_bank_test(openram_test):
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def runTest(self):
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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