mirror of https://github.com/VLSIDA/OpenRAM.git
Added seprate return for power values of lib.
This commit is contained in:
parent
d195df682d
commit
233acc3fcc
|
|
@ -389,11 +389,12 @@ class delay():
|
|||
data = {"min_period1": min_period1, # period in ns
|
||||
"delay1": delay1, # delay in s
|
||||
"min_period0": min_period0,
|
||||
"delay0": delay0,
|
||||
"Read_Power": read_power,
|
||||
"Write_Power": write_power
|
||||
"delay0": delay0
|
||||
}
|
||||
return data
|
||||
power = {"Read_Power": read_power,
|
||||
"Write_Power": write_power
|
||||
}
|
||||
return data, power
|
||||
|
||||
|
||||
def obtain_cycle_times(self, slow_period, fast_period):
|
||||
|
|
|
|||
|
|
@ -61,12 +61,12 @@ class lib:
|
|||
probe_address = "1" * self.addr_size
|
||||
probe_data = self.word_size - 1
|
||||
|
||||
data = self.d.analyze(probe_address, probe_data)
|
||||
for i in data.keys()[0:3]:
|
||||
data , power = self.d.analyze(probe_address, probe_data)
|
||||
for i in data.keys():
|
||||
data[i] = ch.round_time(data[i])
|
||||
|
||||
|
||||
self.write_data_bus(data, times)
|
||||
self.write_data_bus(data, power, times)
|
||||
self.write_addr_bus(times)
|
||||
self.write_control_pins(times)
|
||||
self.write_clk(data)
|
||||
|
|
@ -199,7 +199,7 @@ class lib:
|
|||
|
||||
|
||||
|
||||
def write_data_bus(self, data, times):
|
||||
def write_data_bus(self, data, power, times):
|
||||
""" Adds data bus timing results."""
|
||||
self.lib.write(" bus(DATA){\n")
|
||||
self.lib.write(" bus_type : DATA; \n")
|
||||
|
|
@ -217,10 +217,10 @@ class lib:
|
|||
self.lib.write(" internal_power(){\n")
|
||||
self.lib.write(" when : \"OEb & !clk\"; \n")
|
||||
self.lib.write(" rise_power(INPUT_BY_TRANS_FOR_SIGNAL){\n")
|
||||
self.lib.write(" values(\"{0}\");\n".format(data["Write_Power"]* 1e3))
|
||||
self.lib.write(" values(\"{0}\");\n".format(power["Write_Power"]* 1e3))
|
||||
self.lib.write(" }\n")
|
||||
self.lib.write(" fall_power(INPUT_BY_TRANS_FOR_SIGNAL){\n")
|
||||
self.lib.write(" values(\"{0}\");\n".format(data["Write_Power"]* 1e3))
|
||||
self.lib.write(" values(\"{0}\");\n".format(power["Write_Power"]* 1e3))
|
||||
self.lib.write(" }\n")
|
||||
self.lib.write(" }\n")
|
||||
self.write_timing(times)
|
||||
|
|
@ -231,10 +231,10 @@ class lib:
|
|||
self.lib.write(" internal_power(){\n")
|
||||
self.lib.write(" when : \"!OEb & !clk\"; \n")
|
||||
self.lib.write(" rise_power(INPUT_BY_TRANS_FOR_SIGNAL){\n")
|
||||
self.lib.write(" values(\"{0}\");\n".format(data["Read_Power"]* 1e3))
|
||||
self.lib.write(" values(\"{0}\");\n".format(power["Read_Power"]* 1e3))
|
||||
self.lib.write(" }\n")
|
||||
self.lib.write(" fall_power(INPUT_BY_TRANS_FOR_SIGNAL){\n")
|
||||
self.lib.write(" values(\"{0}\");\n".format(data["Read_Power"]* 1e3))
|
||||
self.lib.write(" values(\"{0}\");\n".format(power["Read_Power"]* 1e3))
|
||||
self.lib.write(" }\n")
|
||||
self.lib.write(" }\n")
|
||||
self.lib.write(" timing(){ \n")
|
||||
|
|
@ -293,7 +293,7 @@ class lib:
|
|||
self.lib.write(" clock : true;\n")
|
||||
self.lib.write(" direction : input; \n")
|
||||
self.lib.write(" capacitance : {0}; \n".format(tech.spice["FF_in_cap"]))
|
||||
min_pulse_width = (ch.round_time(data["min_period1"]) + ch.round_time(data["min_period0"]))/2
|
||||
min_pulse_width = (ch.round_time(data["min_period1"]) + ch.round_time(data["min_period0"]))/2.0
|
||||
min_period = ch.round_time(data["min_period1"]) + ch.round_time(data["min_period0"])
|
||||
self.lib.write(" timing(){ \n")
|
||||
self.lib.write(" timing_type :\"min_pulse_width\"; \n")
|
||||
|
|
|
|||
Loading…
Reference in New Issue