Changed # of address signals to reflect # of ports in delay

compiler/characterizer/delay.py

@@ -170,6 +170,18 @@ class delay():
         for i in range(self.addr_size):
             self.stim.gen_constant(sig_name="A[{0}]".format(i),
                                    v_val=0)
+        for readwrite_addr in range(OPTS.rw_ports):
+            for i in range(self.addr_size):
+                self.stim.gen_constant(sig_name="A_RWP{0}[{1}]".format(readwrite_addr,i),
+                                   v_val=0)
+        for write_addr in range(OPTS.w_ports):
+            for i in range(self.addr_size):
+                self.stim.gen_constant(sig_name="A_WP{0}[{1}]".format(write_addr,i),
+                                   v_val=0)
+        for read_addr in range(OPTS.r_ports):
+            for i in range(self.addr_size):
+                self.stim.gen_constant(sig_name="A_RP{0}[{1}]".format(read_addr,i),
+                                   v_val=0)
 
         # generate control signals
         self.sf.write("\n* Generation of control signals\n")
@@ -802,9 +814,18 @@ class delay():
         Generates the address inputs for a simulation timing test. 
         This alternates between all 1's and all 0's for the address.
         """
-        for i in range(self.addr_size):
-            sig_name = "A[{0}]".format(i)
-            self.stim.gen_pwl(sig_name, self.cycle_times, self.addr_values[i], self.period, self.slew, 0.05)
+        for readwrite_addr in range(OPTS.rw_ports):
+            for i in range(self.addr_size):
+                sig_name = "A_RWP{0}[{1}]".format(readwrite_addr,i)
+                self.stim.gen_pwl(sig_name, self.cycle_times, self.addr_values[i], self.period, self.slew, 0.05)
+        for write_addr in range(OPTS.w_ports):
+            for i in range(self.addr_size):
+                sig_name = "A_WP{0}[{1}]".format(write_addr,i)
+                self.stim.gen_pwl(sig_name, self.cycle_times, self.addr_values[i], self.period, self.slew, 0.05)
+        for read_addr in range(OPTS.r_ports):
+            for i in range(self.addr_size):
+                sig_name = "A_RP{0}[{1}]".format(read_addr,i)
+                self.stim.gen_pwl(sig_name, self.cycle_times, self.addr_values[i], self.period, self.slew, 0.05)
 
 
     def gen_control(self):

compiler/characterizer/stimuli.py

@@ -40,8 +40,18 @@ class stimuli():
         for write_input in range(OPTS.w_ports):
             for i in range(dbits):
                 self.sf.write("DIN_WP{0}[{1}] ".format(write_input, i))
-        for i in range(abits):
-            self.sf.write("A[{0}] ".format(i))
+        
+        for readwrite_addr in range(OPTS.rw_ports):
+            for i in range(abits):
+                self.sf.write("A_RWP{0}[{1}] ".format(readwrite_addr,i))
+        for write_addr in range(OPTS.w_ports):
+            for i in range(abits):
+                self.sf.write("A_WP{0}[{1}] ".format(write_addr,i))
+        for read_addr in range(OPTS.r_ports):
+            for i in range(abits):
+                self.sf.write("A_RP{0}[{1}] ".format(read_addr,i))     
+
+            
         for i in tech.spice["control_signals"]:
             self.sf.write("{0} ".format(i))
         self.sf.write("{0} ".format(tech.spice["clk"]))

compiler/example_config_freepdk45.py

@@ -14,6 +14,6 @@ output_name = "sram_2_16_1_freepdk45"
 #bitcell = "pbitcell"
 
 # These are the configuration parameters
-rw_ports = 2
-r_ports = 2
-w_ports = 2
+#rw_ports = 2
+#r_ports = 2
+#w_ports = 2