mirror of https://github.com/VLSIDA/OpenRAM.git
Add some router tests for SCMOS. Not all are there. Found bug in off-grid pin access for one test that is still there.
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@ -56,8 +56,7 @@ class no_blockages_test(unittest.TestCase):
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r.route(layer_stack,src="A",dest="B")
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r.add_route(self)
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r = routing("test1", "01_no_blockages_test")
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r = routing("test1", "01_no_blockages_test_{0}".format(OPTS.tech_name))
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self.local_check(r)
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# fails if there are any DRC errors on any cells
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@ -56,7 +56,7 @@ class blockages_test(unittest.TestCase):
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r.route(layer_stack,src="A",dest="B")
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r.add_route(self)
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r = routing("test1", "02_blockages_test")
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r = routing("test1", "02_blockages_test_{0}".format(OPTS.tech_name))
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self.local_check(r)
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# fails if there are any DRC errors on any cells
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@ -55,7 +55,7 @@ class same_layer_pins_test(unittest.TestCase):
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r.route(layer_stack,src="A",dest="B")
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r.add_route(self)
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r = routing("test1", "03_same_layer_pins_test")
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r = routing("test1", "03_same_layer_pins_test_{0}".format(OPTS.tech_name))
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self.local_check(r)
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@ -57,9 +57,7 @@ class diff_layer_pins_test(unittest.TestCase):
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r.route(layer_stack,src="A",dest="B")
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r.add_route(self)
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r = routing("test1", "04_diff_layer_pins_test")
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r = routing("test1", "04_diff_layer_pins_test_{0}".format(OPTS.tech_name))
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self.local_check(r)
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# fails if there are any DRC errors on any cells
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@ -62,7 +62,7 @@ class two_nets_test(unittest.TestCase):
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r = routing("test1", "05_two_nets_test")
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r = routing("test1", "05_two_nets_test_{0}".format(OPTS.tech_name))
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self.local_check(r)
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# fails if there are any DRC errors on any cells
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@ -60,9 +60,12 @@ class pin_location_test(unittest.TestCase):
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#r.route(layer_stack,src="A",dest="B")
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r.add_route(self)
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r = routing("test1", "01_no_blockages_test")
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self.local_check(r)
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# This only works for freepdk45 since the coordinates are hard coded
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if OPTS.tech_name == "freepdk45":
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r = routing("test1", "06_pin_location_test_{0}".format(OPTS.tech_name))
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self.local_check(r)
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else:
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debug.warning("This test does not support technology {0}".format(OPTS.tech_name))
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# fails if there are any DRC errors on any cells
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globals.end_openram()
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@ -12,7 +12,7 @@ import calibre
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OPTS = globals.OPTS
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class big_scmos_test(unittest.TestCase):
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class big_test(unittest.TestCase):
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"""
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Simplest two pin route test with no blockages using the pin locations instead of labels.
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"""
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@ -58,11 +58,12 @@ class big_scmos_test(unittest.TestCase):
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r.route(layer_stack,src="A",dest="B")
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r.add_route(self)
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# This test only runs on scn3me_subm tech
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if OPTS.tech_name=="scn3me_subm":
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r = routing("test1", "07_big_scmos_test")
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r = routing("test1", "07_big_test_{0}".format(OPTS.tech_name))
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self.local_check(r)
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else:
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debug.warning("Test must be run in scn3me_subm")
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debug.warning("This test does not support technology {0}".format(OPTS.tech_name))
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# fails if there are any DRC errors on any cells
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globals.end_openram()
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