mirror of https://github.com/VLSIDA/OpenRAM.git
Update replica bitline test for new parameters. Add small test and a larger test.
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@ -21,10 +21,18 @@ class replica_bitline_test(openram_test):
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import replica_bitline
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debug.info(2, "Testing RBL")
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a = replica_bitline.replica_bitline(13)
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stages=4
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rows=13
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debug.info(2, "Testing RBL with {0} FO4 stages, {1} rows".format(stages,rows))
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a = replica_bitline.replica_bitline(stages,rows)
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self.local_check(a)
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stages=8
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rows=100
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debug.info(2, "Testing RBL with {0} FO4 stages, {1} rows".format(stages,rows))
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a = replica_bitline.replica_bitline(stages,rows)
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self.local_check(a)
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OPTS.check_lvsdrc = True
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globals.end_openram()
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