mirror of https://github.com/VLSIDA/OpenRAM.git
Convert print to functional type call like Python 3. Perform error checking that requires Python >2.7 <3.0 for better error checking.
This commit is contained in:
Matt Guthaus
parent
6e90bf0d6d
commit
8a821e13ac
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@ -13,20 +13,20 @@ def check(check,str):
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(frame, filename, line_number, function_name, lines,
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index) = inspect.getouterframes(inspect.currentframe())[1]
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if not check:
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print "ERROR: file ", os.path.basename(filename), ": line ", line_number, ": ", str
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print("ERROR: file {0}: line {1}: {2}".format(os.path.basename(filename),line_number,str))
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sys.exit(-1)
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def error(str,return_value=None):
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(frame, filename, line_number, function_name, lines,
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index) = inspect.getouterframes(inspect.currentframe())[1]
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print "ERROR: file ", os.path.basename(filename), ": line ", line_number, ": ", str
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print("ERROR: file {0}: line {1}: {2}".format(os.path.basename(filename),line_number,str))
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if return_value:
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sys.exit(return_value)
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def warning(str):
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(frame, filename, line_number, function_name, lines,
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index) = inspect.getouterframes(inspect.currentframe())[1]
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print "WARNING: file ", os.path.basename(filename), ": line ", line_number, ": ", str
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print("WARNING: file {0}: line {1}: {2}".format(os.path.basename(filename),line_number,str))
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def info(lev, str):
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@ -34,6 +34,6 @@ def info(lev, str):
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if (OPTS.debug_level >= lev):
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frm = inspect.stack()[1]
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mod = inspect.getmodule(frm[0])
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print "\n[", frm[0].f_code.co_name, "]: ", str
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print("\n[{0}]: {1}".format(frm[0].f_code.co_name,str))
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# This sometimes gets a NoneType mod...
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# print "[" , mod.__name__ , "]: ", str
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@ -87,18 +87,18 @@ def print_banner():
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if not OPTS.print_banner:
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return
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print "|==============================================================================|"
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print("|==============================================================================|")
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name = "OpenRAM Compiler v"+VERSION
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print "|=========" + name.center(60) + "=========|"
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print "|=========" + " ".center(60) + "=========|"
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print "|=========" + "VLSI Design and Automation Lab".center(60) + "=========|"
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print "|=========" + "University of California Santa Cruz CE Department".center(60) + "=========|"
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print "|=========" + " ".center(60) + "=========|"
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print "|=========" + "VLSI Computer Architecture Research Group".center(60) + "=========|"
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print "|=========" + "Oklahoma State University ECE Department".center(60) + "=========|"
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print "|=========" + " ".center(60) + "=========|"
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print "|=========" + OPTS.openram_temp.center(60) + "=========|"
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print "|==============================================================================|"
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print("|=========" + name.center(60) + "=========|")
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print("|=========" + " ".center(60) + "=========|")
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print("|=========" + "VLSI Design and Automation Lab".center(60) + "=========|")
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print("|=========" + "University of California Santa Cruz CE Department".center(60) + "=========|")
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print("|=========" + " ".center(60) + "=========|")
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print("|=========" + "VLSI Computer Architecture Research Group".center(60) + "=========|")
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print("|=========" + "Oklahoma State University ECE Department".center(60) + "=========|")
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print("|=========" + " ".center(60) + "=========|")
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print("|=========" + OPTS.openram_temp.center(60) + "=========|")
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print("|==============================================================================|")
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def init_openram(config_file):
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@ -214,18 +214,18 @@ def setup_paths():
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# make the directory if it doesn't exist
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try:
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os.makedirs(OPTS.openram_temp, 0750)
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os.makedirs(OPTS.openram_temp, 0o750)
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except OSError as e:
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if e.errno == 17: # errno.EEXIST
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os.chmod(OPTS.openram_temp, 0750)
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os.chmod(OPTS.openram_temp, 0o750)
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# Don't delete the output dir, it may have other files!
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# make the directory if it doesn't exist
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try:
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os.makedirs(OPTS.output_path, 0750)
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os.makedirs(OPTS.output_path, 0o750)
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except OSError as e:
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if e.errno == 17: # errno.EEXIST
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os.chmod(OPTS.output_path, 0750)
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os.chmod(OPTS.output_path, 0o750)
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@ -109,7 +109,6 @@ class hierarchical_predecode2x4(hierarchical_predecode):
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return self.rail_height
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def delay(self, slope, load = 0.0 ):
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#print "pre2x4 consist:"
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# A -> B
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a_t_b_delay = self.inv.delay(slope=slope,load = self.nand.input_load())
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@ -120,7 +119,6 @@ class hierarchical_predecode2x4(hierarchical_predecode):
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# Z -> out
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a_t_out_delay = self.inv.delay(slope=b_t_z_delay.slope,load = load)
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result = result + a_t_out_delay
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#print "end of pre2x4"
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return result
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def input_load(self):
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@ -31,7 +31,7 @@ import debug
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# required positional args for using openram main exe
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if len(args) < 1:
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print globals.USAGE
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print(globals.USAGE)
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sys.exit(2)
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globals.print_banner()
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@ -61,14 +61,14 @@ if (OPTS.output_name == ""):
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debug.info(1, "Output file is " + OPTS.output_name + ".(sp|gds|v|lib|lef)")
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print "Technology: %s" % (OPTS.tech_name)
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print "Word size: {0}\nWords: {1}\nBanks: {2}".format(word_size,num_words,num_banks)
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print("Technology: {0}".format(OPTS.tech_name))
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print("Word size: {0}\nWords: {1}\nBanks: {2}".format(word_size,num_words,num_banks))
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# only start importing modules after we have the config file
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import calibre
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import sram
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print "Start: ", datetime.datetime.now()
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print("Start: {0}".format(datetime.datetime.now()))
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# import SRAM test generation
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s = sram.sram(word_size=word_size,
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@ -79,16 +79,16 @@ s = sram.sram(word_size=word_size,
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# Measure design area
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# Not working?
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#cell_size = s.gds.measureSize(s.name)
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#print "Area:", cell_size[0] * cell_size[1]
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#print("Area:", cell_size[0] * cell_size[1])
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# Output the files for the resulting SRAM
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spname = OPTS.output_path + s.name + ".sp"
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print "SP: Writing to {0}".format(spname)
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print("SP: Writing to {0}".format(spname))
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s.sp_write(spname)
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gdsname = OPTS.output_path + s.name + ".gds"
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print "GDS: Writing to {0}".format(gdsname)
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print("GDS: Writing to {0}".format(gdsname))
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s.gds_write(gdsname)
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# Run Characterizer on the design
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@ -101,21 +101,21 @@ if OPTS.use_pex:
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# geenrate verilog
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import verilog
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vname = OPTS.output_path + s.name + ".v"
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print "Verilog: Writing to {0}".format(vname)
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print("Verilog: Writing to {0}".format(vname))
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verilog.verilog(vname,s)
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# generate LEF
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import lef
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lefname = OPTS.output_path + s.name + ".lef"
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print "LEF: Writing to {0}".format(lefname)
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print("LEF: Writing to {0}".format(lefname))
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lef.lef(gdsname,lefname,s)
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# generate lib
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import lib
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libname = OPTS.output_path + s.name + ".lib"
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print "LIB: Writing to {0}".format(libname)
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print("LIB: Writing to {0}".format(libname))
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lib.lib(libname,s,sram_file)
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globals.end_openram()
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print "End: ", datetime.datetime.now()
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print("End: {0}".format(datetime.datetime.now()))
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