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1601 Commits

Author SHA1 Message Date
Matt Guthaus e040fd12f9 Bitcell and bitcell array can be named the same. 2018-11-16 12:00:23 -08:00
Matt Guthaus 5e0eb609da Check for single top-level structure in vlsiLayout. Don't allow dff_inv and dff_buf to have same names. 2018-11-16 11:48:41 -08:00
Matt Guthaus 68ac7e5955 Fix offset of column decoder with new mirroring 2018-11-15 17:27:58 -08:00
Matt Guthaus 712b71c5ca Mirror port 1 column decoder in X and Y 2018-11-15 15:26:59 -08:00
Jennifer Eve Sowash c73004de35 Merge branch 'pdriver' of https://github.com/VLSIDA/PrivateRAM into pdriver 2018-11-15 14:06:38 -08:00
Jesse Cirimelli-Low 59c0421804 merge dev into datasheet_gen; fixed merge conflict in hierarchy_design.py 2018-11-15 10:45:33 -08:00
Matt Guthaus 21d111acfe Move wordline driver clock line below decoder. Fix port 1 clock route DRC. 2018-11-15 10:30:38 -08:00
Hunter Nichols 6e47de3f9b Separated relative delay into rise/fall. 2018-11-14 23:34:53 -08:00
Matt Guthaus 66982a9283 Only add second port if it is specified. 2018-11-14 17:11:23 -08:00
Matt Guthaus 2fd86958a8 Merge branch 'multiport_layout' of ssh://scone/home/mrg/openram into multiport_layout 2018-11-14 17:07:01 -08:00
Matt Guthaus 3cfefa784f Fix run-time bug in combine adjacent pins for supply router 2018-11-14 17:06:12 -08:00
Matt Guthaus 3221d3e744 Add initial support and unit tests for 2 port SRAM 2018-11-14 17:05:23 -08:00
Hunter Nichols e9f6566e59 Fixed merge conflict, moved control logic mod instantiation, removed some commented out code. 2018-11-14 13:53:27 -08:00
Matt Guthaus 6ac5adaeca Separate multiport replica bitline from regular replica bitline test 2018-11-14 11:41:09 -08:00
Matt Guthaus 2f6300c7a0 Fix date/time formatting to remove fraction seconds. 2018-11-14 10:31:33 -08:00
Matt Guthaus 18d874a96a Fix error in iterative implementation of combine_classes 2018-11-14 10:05:04 -08:00
Hunter Nichols 8b6a28b6fd Changed scmos bitcell 1rw,1r to have same tx widths as pbitcell. 2018-11-13 22:24:18 -08:00
Matt Guthaus 4ebb8a26c4 Disable debug statements. 2018-11-13 17:43:08 -08:00
Matt Guthaus ddb4cabfe1 Change recursive equivalence class detection to iterative. 2018-11-13 17:42:06 -08:00
Matt Guthaus ff0a7851b7 Fix error when DRC is disabled so it doesn't initialize. 2018-11-13 17:41:32 -08:00
Jesse Cirimelli-Low fa27d647d2 Flask directory upload POC, embed datasheet.info in html comment for parser reuse 2018-11-13 17:29:43 -08:00
Matt Guthaus ce74827f24 Add new option to enable inline checks at each level of hierarchy. Default is off. 2018-11-13 16:51:19 -08:00
Matt Guthaus 01ceedb348 Only check number of ports when doing layout. 2018-11-13 16:42:25 -08:00
Matt Guthaus bc7e74f571 Add multiport bank test 2018-11-13 16:06:21 -08:00
Matt Guthaus aa779a7f82 Initial two port bank in SCMOS 2018-11-13 16:05:22 -08:00
Jennifer Sowash b6f1409fb9 Testing to ensure branch is up to date with dev. Added 04_pbuf_test.py and made changes to pbuf.py to align with comments. 2018-11-12 13:24:27 -08:00
Jennifer Sowash b366d88041 Merge branch 'dev' into pdriver 2018-11-12 11:30:37 -08:00
Jennifer Sowash 82abd32785 Added pbuf.py to create a single buffer. 2018-11-12 09:53:21 -08:00
Hunter Nichols 6f6d45f025 Merge branch 'dev' into multiport_characterization 2018-11-11 23:47:49 -08:00
Matt Guthaus 732f35a362 Change channel router to route from bottom up to simplify code. 2018-11-11 12:25:53 -08:00
Matt Guthaus 791d74f63a Fix wrong exception handling that depended on order. Replaced with if/else instead. 2018-11-11 12:02:42 -08:00
Jesse Cirimelli-Low 0dd97e54dd reverted css to UCSC colors, fixed header styling, added placeholder openram logo 2018-11-11 09:27:07 -08:00
Jesse Cirimelli-Low 4227a7886a Merge branch 'dev' into datasheet_gen 2018-11-11 07:27:42 -08:00
Jesse Cirimelli-Low 91a63fb5c2 Merge branch 'dev' 2018-11-11 07:24:03 -08:00
Jesse Cirimelli-Low 5c4ee911aa added another VLSI logo and fixed control port numbering 2018-11-11 07:22:13 -08:00
Jesse Cirimelli-Low aadf160ce4 added missing space in sheet 2018-11-11 06:05:14 -08:00
Jesse Cirimelli-Low 4ba07e4b94 Complete rewrite of parser, all ports (except clock) added on multiport sheets 2018-11-10 20:23:26 -08:00
Matt Guthaus 5cbbd5e4ca Comment out regress CI debug code 2018-11-10 13:44:36 -08:00
Matt Guthaus 6c17734712 Add testutil archive on failed tests for debug 2018-11-10 11:54:28 -08:00
Jesse Cirimelli-Low 62f8d26ec6 Merge branch 'dev' into datasheet_gen 2018-11-10 10:58:35 -08:00
Matt Guthaus 65b6bfd5e7 Change os to shutils 2018-11-10 10:06:33 -08:00
Matt Guthaus 3b6b93e2ca Save gds file in testutils when fail to figure out randomness in regression CI 2018-11-10 10:05:27 -08:00
Hunter Nichols bad55cfd05 Merged with dev. Fixed merge conflict. 2018-11-09 17:18:19 -08:00
Hunter Nichols ea1a1c7705 Added delay chain resizing based on analytical delay. 2018-11-09 17:14:52 -08:00
Matt Guthaus 550d5cc729 Fix path to config file in test 30 2018-11-09 16:33:08 -08:00
Matt Guthaus de61630962 Expand blocked pins to neighbor grid cells. 2018-11-09 14:25:10 -08:00
Matt Guthaus c5b408ae2d Add router output message 2018-11-09 11:10:40 -08:00
Matt Guthaus c01effc819 Adjust ptx positions in precharge to be under the bl rail 2018-11-09 10:26:15 -08:00
Matt Guthaus ac7229f8d3 Move vdd pin in precharge inside cell 2018-11-09 10:11:24 -08:00
Matt Guthaus cc619084c7 Clean up psingle_bank_test 2018-11-09 09:34:34 -08:00
Matt Guthaus 21f5fb0870 precharge bl is on metal2 only. simplify via position code. 2018-11-09 09:11:00 -08:00
Matt Guthaus 6aff552c0a Merge branch 'multiport_layout' of https://github.com/VLSIDA/PrivateRAM into multiport_layout 2018-11-09 08:53:27 -08:00
Matt Guthaus 8f3fa0e2f6 Fix blocked pin debug output. 2018-11-09 08:52:05 -08:00
Hunter Nichols 8957c556db Added sense amp enable delay calculation. 2018-11-08 23:54:18 -08:00
Hunter Nichols b8061d3a4e Added initial code for determining the logical effort delay of the wordline. 2018-11-08 23:54:18 -08:00
Jesse Cirimelli-Low d6c0247ff2 added area to datasheet 2018-11-08 21:30:17 -08:00
Jesse Cirimelli-Low 30bffdf1b4 Merge branch 'dev' into datasheet_gen 2018-11-08 19:26:00 -08:00
Matt Guthaus 9c8d5395ff Update leakage data for scn4m 2018-11-08 18:16:01 -08:00
Matt Guthaus 31eff6f24e Merge branch 'dev' into multiport_layout 2018-11-08 18:00:28 -08:00
Matt Guthaus 5d684b02e0 Leakage changed in ngspice test. 2018-11-08 18:00:09 -08:00
Matt Guthaus 71177d0b70 Fixed small bugs with new port index stuff and layout. 2018-11-08 17:40:22 -08:00
Matt Guthaus d03c9d5294 Fix write bl name list in replica bitline 2018-11-08 17:02:20 -08:00
Matt Guthaus fd5cd675ac Horizontal increments top down. 2018-11-08 17:01:57 -08:00
Matt Guthaus 18fbf30b46 Convert col decoder select routing to channel route. 2018-11-08 16:53:58 -08:00
Matt Guthaus e28978180f Vertical channel routes go from left right. Horizontal go bottom up. 2018-11-08 16:49:02 -08:00
Matt Guthaus ef2ed9a92c Simplify bl and br name lists. 2018-11-08 15:48:49 -08:00
Matt Guthaus 5d733154e9 Refactor bank to allow easier multiport. 2018-11-08 15:18:51 -08:00
Matt Guthaus 7b10e3bfec Convert port index lists to three simple lists. 2018-11-08 12:19:40 -08:00
Matt Guthaus b25650eb07 Netlist only mode for ngspice delay test 2018-11-08 12:19:06 -08:00
Matt Guthaus dd5b2a5b59 Fix missing fail when non-list item doesn't match. 2018-11-08 12:16:59 -08:00
Michael Timothy Grimes 7c3375fd4b Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-11-08 09:59:52 -08:00
Matt Guthaus 929eae4a23 Document why sense amp is 8x isolation transistor 2018-11-07 16:09:50 -08:00
Matt Guthaus 5dfba21acc Change tx mux size back to 8. Document why it was chosen. 2018-11-07 16:03:48 -08:00
Matt Guthaus 3d2abc0873 Change default col mux size to 2. Add some comments. 2018-11-07 15:43:08 -08:00
Matt Guthaus ad7fe1be51 Clean up code formatting. 2018-11-07 14:52:03 -08:00
Matt Guthaus 4e232c49ad Update precharge cell for multiport. 
Comment out pbitcell tests.
Add bitcell_1rw_1r test.
Move bitcell horizontal routing to metal1.
Extend precharge height for stacking.
 2018-11-07 14:46:51 -08:00
Matt Guthaus 050035ae8d Add magic/netgen to example config 2018-11-07 13:54:00 -08:00
Matt Guthaus 2e5ae70391 Enable psram 1rw 2mux layout test. 2018-11-07 13:37:08 -08:00
Matt Guthaus f04e76a54f Allow multiple must-connect pins with the same label. 2018-11-07 13:05:13 -08:00
Matt Guthaus 8d753b5ac7 Primitive cells only keep the largest pin shape. 2018-11-07 11:58:31 -08:00
Matt Guthaus 1fe767343e Reimplement gdsMill pin functions so they are run once when a GDS is loaded. Get pins is now a table lookup. 2018-11-07 11:31:44 -08:00
Jesse Cirimelli-Low 00dd6ddfd0 Merge branch 'dev' into datasheet_gen 2018-11-07 10:47:37 -08:00
Jesse Cirimelli-Low 781bd13cc1 Merge branch 'dev' into datasheet_gen 2018-11-07 10:08:45 -08:00
Matt Guthaus 485590052a Merge branch 'supply_routing' of https://github.com/VLSIDA/PrivateRAM into supply_routing 2018-11-06 07:56:57 -08:00
Matt Guthaus 279fe4d103 Merge branch 'dev' into supply_routing 2018-11-06 07:56:29 -08:00
Matt Guthaus 86a8dca584 Merge branch 'dev' into supply_routing 2018-11-05 15:04:57 -08:00
Hunter Nichols ff169fcb2b Merged with dev, fixed config file conflict. 2018-11-05 14:58:52 -08:00
Hunter Nichols 4c26dede23 Unskipped functional tests and increases the number of ports on pbitcell functional tests. 2018-11-05 14:56:22 -08:00
Matt Guthaus 831e454b34 Remove redundant DRC run in magic. 2018-11-05 13:30:42 -08:00
Matt Guthaus 37b81c0af1 Remove options from example config files 2018-11-05 12:47:47 -08:00
Matt Guthaus 02bafb4757 Merge remote-tracking branch 'origin/dev' into supply_routing 2018-11-05 12:44:46 -08:00
Hunter Nichols 9744bc516a Merge branch 'dev' into multiport_characterization 2018-11-05 10:40:29 -08:00
Matt Guthaus ce94366a1d Skip all 4mux and 8mux tests until we solve teh simulation timing bug. 2018-11-05 09:50:44 -08:00
Michael Timothy Grimes 3c9821991b Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-11-05 08:56:19 -08:00
Matt Guthaus 38dab77bfc Add fixed seed to functional test during unit tests. Skip non-working tests after fixed seed. 2018-11-03 10:53:09 -07:00
Matt Guthaus 5d2df76ef5 Skip 4mux test 2018-11-03 10:16:22 -07:00
Matt Guthaus 5ecfa88d2a Pad the routing grid by a few tracks to add an extra rail 2018-11-02 17:35:35 -07:00
Matt Guthaus a3666d82ab Reduce verbosity of level 1 debug. 2018-11-02 17:30:28 -07:00
Hunter Nichols 7461f2b1bf Merged with dev. 2018-11-02 17:22:09 -07:00
Hunter Nichols f05865b307 Fixed drc issues with replica bitline test. 2018-11-02 17:16:41 -07:00
Matt Guthaus f8e761313a Merge branch 'dev' into supply_routing 2018-11-02 16:39:49 -07:00
Matt Guthaus 852bfbc031 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2018-11-02 16:34:36 -07:00
Matt Guthaus 6dd959b638 Fix error in 8mux test. Fix comment in all tests. 2018-11-02 16:34:26 -07:00
Matt Guthaus ad1d3a3c78 Use default grid costs again. 2018-11-02 16:04:56 -07:00
Matt Guthaus 3950a9feff Merge branch 'supply_routing' into dev 2018-11-02 15:31:29 -07:00
Matt Guthaus 74c3de2812 Remove diagonal routing bug. Cleanup. 2018-11-02 14:57:40 -07:00
Matt Guthaus ac203d987c Merge branch 'supply_routing' into dev 2018-11-02 11:50:46 -07:00
Matt Guthaus 866eaa8b02 Add debug message when routes are diagonal. 2018-11-02 11:50:28 -07:00
Matt Guthaus 4d30f214da Add expanded blockages for paths an enclosures to handle wide metal spacing rules. 2018-11-02 11:11:32 -07:00
Michael Timothy Grimes 6711630463 Altering the routing slightly in the column mux to give the gnd contacts a wider berth. This prevents drc errors when the bitlines are close to the edge of the cell. 2018-11-02 05:59:47 -07:00
Hunter Nichols 642dc8517c Added no mux functional test for 1rw+1r. Delay characterization also works for the custom cell as well. 2018-11-01 14:05:55 -07:00
Jesse Cirimelli-Low 3fa1d5522e added DRC/LVS error count to datasheet 2018-11-01 14:02:33 -07:00
Hunter Nichols b00fc040a3 Added replica 1rw+1r cell python modules. Also added drc/lvs checks in replica bitline, but test is failing due to pin error in freepdk45 and metal spacing error in scmos. 2018-11-01 12:29:49 -07:00
Matt Guthaus b24c8a42a1 Remove redundant pins in pin_group constructor. Clean up some code and comments. 2018-11-01 11:31:24 -07:00
Michael Timothy Grimes dc96d86082 Optimizations to pbitcell spacings 2018-11-01 07:58:20 -07:00
Matt Guthaus 2eedc703d1 Rename function in pin_group 2018-10-31 16:13:28 -07:00
Matt Guthaus c511d886bf Added new enclosure connector algorithm using edge sorting. 2018-10-31 15:35:39 -07:00
Jesse Cirimelli-Low ce5001e0af added config file to datasheet and output files 2018-10-31 12:29:13 -07:00
Jesse Cirimelli-Low c3d7e24df9 fixed broken links when -o flag set 2018-10-31 09:34:36 -07:00
Matt Guthaus 673027ac8c Moved assert to check out_path earlier. 
Preserve temporary output directory with -d option.
 2018-10-31 09:37:47 -07:00
Hunter Nichols 9321f0461b Fixed error in control logic test. Added gds/sp for replica cell 1rw+1r. 2018-10-31 00:06:34 -07:00
Jesse Cirimelli-Low 5302fd205f fixed some final typos in datasheet 2018-10-30 23:03:05 -07:00
Jesse Cirimelli-Low 70ac2e8aa4 changed css to orange and black for Halloween; fixed CSb timing table in datasheet 2018-10-30 22:56:13 -07:00
Jesse Cirimelli-Low fe196c23a9 added FF timing information 2018-10-30 22:32:19 -07:00
Hunter Nichols e5dcf5d5b1 Altered bitline with heuristic to have a larger delay chain for larger column muxes. Also have to alter the feasible period for functional tests to pass. 2018-10-30 22:19:26 -07:00
Jesse Cirimelli-Low 905f6f8b43 added docstring and renamed some functions 2018-10-30 21:37:30 -07:00
Matt Guthaus fc45242ccb Allow contains to contain copy. Add connectors when pin doesn't overlap grids. 2018-10-30 17:41:29 -07:00
Matt Guthaus 7099ee76e9 Remove blocked grids from pins and secondary grids 2018-10-30 16:52:11 -07:00
Matt Guthaus 1344a8f7f1 Add remove adjacent feature for wide metal spacing 2018-10-30 12:24:13 -07:00
Matt Guthaus c4163d3401 Remove debug statements. 2018-10-29 13:50:56 -07:00
Matt Guthaus fa272be3bd Enumerate more enclosures. 2018-10-29 13:49:29 -07:00
Matt Guthaus cd87df8f76 Clean up enclosure code 2018-10-29 11:27:59 -07:00
Matt Guthaus f19bcace62 Merged in an old stash. 2018-10-29 11:18:12 -07:00
Matt Guthaus b7655eab10 Remove bug for combining pin with multiple other pins in a single iteration 2018-10-29 11:07:02 -07:00
Matt Guthaus bbffec863b Abandon connectors for now and opt for all enclosures 2018-10-29 10:59:22 -07:00
Matt Guthaus 6990773ea1 Add error check requiring non-zero area pin layouts. 2018-10-29 10:32:42 -07:00
Matt Guthaus 851aeae8c4 Add pins_enclosed function to pin_group 2018-10-29 10:28:57 -07:00
Jesse Cirimelli-Low 2da90c4b6a fixed double counting of characterization tuple permutations 2018-10-27 12:04:10 -07:00
Jesse Cirimelli-Low f1fb174b53 fixed bug where netlist_only still produced layout deliverables 2018-10-27 11:21:06 -07:00
Hunter Nichols 3bb8aa7e55 Fixed import errors with mux analytical delay model. 2018-10-26 17:37:25 -07:00
Matt Guthaus 0107e1c050 Reduce verbosity of utils 2018-10-26 13:02:31 -07:00
Matt Guthaus 7d74d34c53 Fix pin_layout contains bug 2018-10-26 10:40:43 -07:00
Matt Guthaus 4ce6b040fd Debugging missing enclosures 2018-10-26 09:25:10 -07:00
Jesse Cirimelli-Low fcfee649d5 moved css into a seperate file to organize and disambiguate docstrings from multiline strings 2018-10-26 07:57:54 -07:00
Hunter Nichols 98a00f985b Changed the analytical delay model to accept multiport options. Little substance to the values generated. 2018-10-26 00:08:13 -07:00
Hunter Nichols 6efe0f56c2 Added gds/sp for scn4m 1rw+1r bitcell. Passes DRC/LVS in both technologies for single and array. 2018-10-26 00:08:13 -07:00
Hunter Nichols 8e243258e4 Added updated 1rw 1r bitcell with a text boundary. Added bitcell array test for the bitcell. 2018-10-26 00:08:12 -07:00
Matt Guthaus 9e5d78cfc2 Fix bug in duplicate remove indices 2018-10-25 14:40:39 -07:00
Matt Guthaus 3407163cf1 Combine adjacent power supply pins finished 2018-10-25 14:25:52 -07:00
Matt Guthaus 0544d02ca2 Refactor router to have pin_groups for pins and router_tech file 2018-10-25 13:36:35 -07:00
Matt Guthaus 3f17679000 Merge remote-tracking branch 'origin' into supply_routing 2018-10-25 09:36:03 -07:00
Matt Guthaus 57fb847d50 Fix check for missing simulator type in characterizer 2018-10-25 09:08:56 -07:00
Matt Guthaus 3d8aeaa732 Run delay and setup/hold tests in netlist_only mode 2018-10-25 09:07:00 -07:00
Matt Guthaus 58de655aac Split functional tests 2018-10-25 08:56:23 -07:00
Michael Timothy Grimes 3202e1eb09 Altering comment code in simulation.py to match the needs of delay.py 2018-10-25 00:58:01 -07:00
Michael Timothy Grimes 40450ac0f5 Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-10-25 00:36:46 -07:00
Michael Timothy Grimes ceab1a5daf Adding debug comments to stim file for functional test and cleaning up comment code in simulation.py. Adding multiple tests for different mux configurations to functional unit tests. 2018-10-25 00:11:00 -07:00
Matt Guthaus b1f3bd97e5 Enable all the 1bank tests. Mostly work in SCMOS. 2018-10-24 17:01:00 -07:00
Matt Guthaus 88f43cc754 Add the minimum pin enclosure that has DRC correct pin connections. 2018-10-24 16:41:33 -07:00
Matt Guthaus 94e5050513 Move overlap functions to pin_layout 2018-10-24 16:13:07 -07:00
Matt Guthaus dc73e8cb60 Odd bug that instances were not properly rotated. 2018-10-24 16:12:27 -07:00
Matt Guthaus 7e2bef624e Continue routing rails in same layer after a blockage 2018-10-24 12:32:27 -07:00
Hunter Nichols a711a5823d Merged dev and fix conflicts in geometry.py 2018-10-24 10:52:22 -07:00
Matt Guthaus cccde193d0 Add ngspice equivalents of RUNLVL 2018-10-24 10:31:27 -07:00
Matt Guthaus 5f17525501 Added run-level option for write_control and enabled fast mode in functional tests 2018-10-24 09:32:44 -07:00
Matt Guthaus 33c716eda8 Rename psram bank test like sram bank testss 2018-10-24 09:08:54 -07:00
Matt Guthaus e90f9be6f5 Move replica bitcells to new bitcells subdir 2018-10-24 09:06:29 -07:00
Hunter Nichols 5c8a00ea1d Fixed pruned golden lib file from error in last commit. 2018-10-24 00:55:55 -07:00
Hunter Nichols da1b003d10 Fixed multiport lib files not generating the correct number of signals. Move setup time from DOUT to DIN in lib file. Altered golden files with these changes. 2018-10-24 00:17:08 -07:00
Hunter Nichols 016604f846 Fixed spacing in golden lib files. Added column mux into analytical model. 2018-10-24 00:16:26 -07:00
Hunter Nichols 53cb4e7f5e Fixed lib files to be syntactically correct with multiport. Fixed issue in geometry.py that prevented netlist_only option from working. 2018-10-22 23:33:01 -07:00
Hunter Nichols 62439bdac6 Fixed merge conflicts with sram.py 2018-10-22 17:29:14 -07:00
Hunter Nichols 4f08062268 Added custom 1rw+1r bitcell. Testing are currently failing. 2018-10-22 17:02:21 -07:00
Michael Timothy Grimes cda2e93cd7 Adding fix to netlist_only mode in geometry.py. Uncommenting functional tests and running both tests in netlist_only mode. 2018-10-22 09:17:03 -07:00
Michael Timothy Grimes 2053a1ca4d Improved debug comments for functional test 2018-10-22 01:09:38 -07:00
Michael Timothy Grimes 1a0568f244 Updating comments and cleaning up code for pbitcell. 2018-10-21 19:10:04 -07:00
Matt Guthaus ab7a83b7a5 Remove old setup.tcl and edit one in tech dir 2018-10-20 15:20:15 -07:00
Matt Guthaus e48e12e8cd Skip non-working 1bank tests for now. 2018-10-20 14:55:11 -07:00
Matt Guthaus 38a8c46034 Change non-preferred route costs. 2018-10-20 14:47:24 -07:00
Matt Guthaus 7591f25a2e Merge branch 'dev' into supply_routing 2018-10-20 14:29:19 -07:00
Matt Guthaus 5276943ba2 Remove temp log file 2018-10-20 14:26:30 -07:00
Matt Guthaus 4c25bb09df Fixed supply end-row via problem by restricting placement 2018-10-20 14:25:32 -07:00
Matt Guthaus f5e68c5c32 Move power pins in hierarchical decoder to be further. Strap rails instead for redundant vias. 2018-10-20 12:54:12 -07:00
Matt Guthaus f9738253c6 Remove warning of track space and floor the space function. 2018-10-20 11:53:52 -07:00
Matt Guthaus a1f2a5befe Convert supply tracks to sets for simpler algorithms. 2018-10-20 10:33:10 -07:00
Matt Guthaus 0aad61892b Supply router working except for off by one rail via error 2018-10-19 14:21:03 -07:00
Matt Guthaus 233a1425e4 Flatten bitcell array in netgen for now. See issue 52 2018-10-19 09:13:17 -07:00
jcirimel 74b806fa38
Merge pull request #54 from VLSIDA/datasheet_gen 
flask_table check fix
 2018-10-18 15:12:04 -07:00
Jesse Cirimelli-Low 1b4383b945 moved flask_table warning from sram.py to datasheet_gen.py 2018-10-18 09:58:19 -07:00
Jesse Cirimelli-Low b9990609bf provides warning on missing flask packages, does not generate html on missing packages 2018-10-18 07:21:03 -07:00
Michael Timothy Grimes a06a0975db Removed L shaped routing from gnd contact to wordlines in replica bitline. Corrected slight DRC errors. Optimizations to pbitcell. 2018-10-18 07:05:47 -07:00
Jesse Cirimelli-Low ab6afb7ca8 fixed html typos, added logo, added placeholder timing and current, began ports section 2018-10-17 19:27:09 -07:00
Matt Guthaus 4bf1e206e2 Merge branch 'dev' into supply_routing 2018-10-17 09:47:18 -07:00
Matt Guthaus 5d6944953b Fix char_result rename collision 2018-10-17 09:38:26 -07:00
Michael Timothy Grimes d6a9ea48ac Working out bugs in psram functional test for SCMOS. Commenting out for now. 2018-10-17 07:45:24 -07:00
Michael Timothy Grimes a27cdb4fbc Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-10-17 07:32:03 -07:00
Michael Timothy Grimes e60deddfea adding 6T transistor size parameters to tech files for use in pbitcell. 2018-10-17 07:28:56 -07:00
Michael Timothy Grimes 69a1560186 Changing the location of the vdd contact in precharge to avoid drc errors when the bitlines are close to the edge of the cell. Correcting replica bitcell function in pbitcell. 2018-10-16 06:57:53 -07:00
Matt Guthaus 5cb3a24b19 Fix supply rail step size to place alternating rails 2018-10-15 13:58:40 -07:00
Matt Guthaus e2cfd382b9 Fix print check regression 2018-10-15 13:23:31 -07:00
Matt Guthaus a165446fa7 First implementation of multiple track spacing wide DRCs in routing grid. 2018-10-15 11:25:51 -07:00
Matt Guthaus d60986e590 Don't skip grid format checks 2018-10-15 11:21:07 -07:00
Matt Guthaus d855d4f1a6 Moving wide metal spacing to routing grid level 2018-10-15 09:59:16 -07:00
Michael Timothy Grimes c8c70401ae Redesign of pbitcell for newer process technolgies. 2018-10-15 06:29:51 -07:00
Matt Guthaus 1c426aad29 Merge remote-tracking branch 'origin/datasheet_gen' into supply_routing 2018-10-12 20:55:57 -07:00
Matt Guthaus ce8c2d983d Update all drc usages to call function type 2018-10-12 14:37:51 -07:00
Jesse Cirimelli-Low afba54a22d added analytical model support, added proper output with sram.py 2018-10-12 13:22:12 -07:00
Matt Guthaus 5e9fe65907 Remove banks from example configs 2018-10-12 10:23:34 -07:00
Matt Guthaus 4932d83afc Add design rules classes for complex design rules 2018-10-12 09:44:36 -07:00
Michael Timothy Grimes d1701b8a2a Removing extra functional test and changing name to a more general form. Spice exe can just be selected from the command line with -s. 2018-10-12 06:29:59 -07:00
Jesse Cirimelli-Low 50cc8023a4 deleted output file left in previous commit 2018-10-11 16:04:43 -07:00
Jesse Cirimelli-Low 35e0ba6fc4 fixed merge error 2018-10-11 16:03:05 -07:00
Jesse Cirimelli-Low cfb5921d98 reorganized code structure 2018-10-11 15:59:06 -07:00
Jesse Cirimelli-Low d142136735 rewrite of redirected print statements to file write 2018-10-11 12:09:50 -07:00
Jesse Cirimelli-Low bc54bc238f removed tabs and fixed bug in which datasheets generated without the characterizer running 2018-10-11 11:18:40 -07:00
Matt Guthaus 297ea81060 Change RBL size to 50% of row size. 2018-10-11 10:39:24 -07:00
Matt Guthaus 1333329dd4 Merge branch 'multiport' into supply_routing 2018-10-11 10:37:10 -07:00
Matt Guthaus f7d1df6ca7 Fix trim spice with new names 2018-10-11 10:36:49 -07:00
Matt Guthaus e759c9350b Skip psram 1 bank 2018-10-11 10:17:50 -07:00
Matt Guthaus a094db9077 Merge branch 'multiport' into supply_routing 2018-10-11 09:56:38 -07:00
Matt Guthaus 823cb04b80 Fix metal4 rules in FreePDK45. Multiport still needs updating. 2018-10-11 09:56:15 -07:00
Matt Guthaus e22e658090 Converted all submodules to use _bit notation instead of [bit] 2018-10-11 09:53:08 -07:00
Matt Guthaus 3f2b7b837d Skip multibank for now too 2018-10-10 16:57:42 -07:00
Matt Guthaus 22b5010734 Skip pmulti which has LVS fail 2018-10-10 16:01:55 -07:00
Matt Guthaus 96d3cacb9c Skip func tests that are failing 2018-10-10 16:00:21 -07:00
Matt Guthaus 9bb1c2bbcf Fix Future Warning for real 2018-10-10 15:58:16 -07:00
Matt Guthaus 13e83e0f1a Separate 1bank tests 2018-10-10 15:58:00 -07:00
Matt Guthaus fa4dd8881c Fix Future warnings comparison to None 2018-10-10 15:47:14 -07:00
Matt Guthaus 6bbf66d55b Rewrote pin enclosure code to better address off grid pins. 
Include only maximal pin enclosure shapes.
Add smallest area connector for off grid pins.
Fix decoder to use add_power_pin code.
Change permissions.
 2018-10-10 15:15:58 -07:00
Hunter Nichols f30e54f33c Cleaned up indexing in variable that records cycle times. 2018-10-10 00:02:03 -07:00
Hunter Nichols 3ac2d29940 Made delay.py a child of simulation.py. Removed duplicate code in delay and changed some in simulation 2018-10-09 17:44:28 -07:00
Hunter Nichols a3bec5518c Put worst case test under the hierarchy of a delay test. Added option for pex option to worst case test. 2018-10-09 00:36:14 -07:00
Hunter Nichols fd806077d2 Added class and test for testing the delay of several bitcells. 2018-10-08 15:50:52 -07:00
Matt Guthaus a2b1d025ab Merge multiport 2018-10-08 11:45:50 -07:00
Matt Guthaus 3244e01ca1 Add copy power pin function 2018-10-08 09:56:39 -07:00
Matt Guthaus 280488b3ad Add M3 supply to pinvbuf 2018-10-08 09:24:16 -07:00
Michael Timothy Grimes 6ef1a3c755 Improvements to functional test. Now will read or write in a random sequence, using randomly generated words and addresses, and using random ports in the multiported cases. Functional test still has some bugs that are being worked out so it will sometimes fail and sometimes not fail. 2018-10-08 06:34:36 -07:00
Jesse Cirimelli-Low 49268b025f fixed /tmp/ typo 2018-10-06 21:17:26 -07:00
Jesse Cirimelli-Low fa979e2d34 initial stages of html documentation generation 2018-10-06 21:15:54 -07:00
Matt Guthaus 06dc910390 Route supply after moving origin 2018-10-06 14:03:00 -07:00
Matt Guthaus 8499983cc2 Add supply router to top-level SRAM. Change get_pins to elegantly fail. 2018-10-06 08:30:38 -07:00
Matt Guthaus 83fd2c0512 Fix openram_temp directory 2018-10-06 08:08:01 -07:00
Matt Guthaus 94ab69ea16 Supply router working, perhaps not efficiently though. 2018-10-05 15:57:34 -07:00
Matt Guthaus eb2304944b Fix .magicrc file name 2018-10-05 08:48:25 -07:00
Matt Guthaus 12cb02a09f Add partial grids as pins. Add previous paths as routing targets. 2018-10-05 08:39:28 -07:00
Matt Guthaus c0ffa9cc7b Clean up magic config file copying. Add warning for missing files. 2018-10-05 08:36:12 -07:00
Matt Guthaus b3fa6b9d52 Make setup.tcl file a technology file 2018-10-05 08:30:25 -07:00
Matt Guthaus 19114fe47f Add commented extraction when running DRC only 2018-10-05 08:18:53 -07:00
Matt Guthaus bb83e5f1be Move clk up in dff arrays for supply pin access 2018-10-05 08:18:38 -07:00
Matt Guthaus 68b30d601e Move bitcells to their own directory in preparation for custom multiport cells. 2018-10-05 08:09:09 -07:00
Hunter Nichols 7b4e001885 Altered web to only be generated for rw ports. 2018-10-04 15:08:12 -07:00
Matt Guthaus c3cd76048b Removed prints. Fixed offset for single track enclosure. 2018-10-04 14:44:25 -07:00
Hunter Nichols 371a57339f Fixed bugs to allow characterization of multiple read ports. Improved some debug messages. 2018-10-04 14:09:09 -07:00
Hunter Nichols 6e0a1b8823 Fixed bugs in power simulations. Made regex raw strings to remove warnings 2018-10-04 14:09:09 -07:00
Hunter Nichols c876bbfe73 Changed characterizer control generation to match recent changes in multiport. 2018-10-04 14:09:09 -07:00
Hunter Nichols 2e322be7f7 Added changes the control logic PWL generation to match changes made in stimuli. 2018-10-04 14:09:09 -07:00
Hunter Nichols 88f2238e03 Multiport variable bug fix and removed unused code. 2018-10-04 14:09:09 -07:00
Hunter Nichols bb79d9a62d Added regex pattern matching to trim_spice to handle multiport. 2018-10-04 14:09:09 -07:00
Hunter Nichols e7f92e67d0 Fixed issues with inst_sram that prevented functional test from running after merge. 2018-10-04 14:09:01 -07:00
Hunter Nichols 6c537c4884 Made stim node names more ngspice friendly for interactive mode. Cleaned up cycle comments. Changed ground names in stim and added related comments. 2018-10-04 14:06:43 -07:00
Hunter Nichols 65edc70cfd Made global names for pins types. Fixed bugs in tests. 2018-10-04 14:06:43 -07:00
Hunter Nichols d2120d6910 Moved pin name creation from stimuli to delay and bug fix in find_feasible_period_one_port 2018-10-04 14:06:34 -07:00
Matt Guthaus 985d04d4b5 Cleanup of router. 
Made offsets in geometry snap to grid.
Changed gds_write to use list for visited flag.
Rewrite self.gds each call in case of any changes.
 2018-10-04 14:04:29 -07:00
Hunter Nichols 4586ed343f Edited lib to support port indexing. Edited tests in reaction to name dict name changes. Cleaned up measurement value generation in delay. 2018-10-04 14:04:08 -07:00
Hunter Nichols ab7d3510b5 Cleaned up result tables to be indexed by port and measurement name. Lib has not been updated, so it crashes there. 2018-10-04 14:04:08 -07:00
Hunter Nichols 346b188372 Improved on some hard coded values which determine the measurements. 2018-10-04 14:04:08 -07:00
Hunter Nichols cfe15d48a4 Added changes to make changing the names of the measurements simple in delay.py. Results in some hardcoded values which is TODO for a fix. 2018-10-04 14:04:08 -07:00
Hunter Nichols aa0d032c78 Cleaned the char_data to fit the previous style. Added print statements to load/slew sims. 2018-10-04 14:04:08 -07:00
Michael Timothy Grimes cf4b216888 Correcting functional inheritance from simulation. 2018-10-04 13:55:59 -07:00
Michael Timothy Grimes e258199fa3 Removing we_b signal from write ports since it is redundant. 2018-10-04 09:31:04 -07:00
Michael Timothy Grimes 34d8a19871 Adding simulation.py for common functions between functional and delay tests. Updating functional test. 2018-10-04 09:29:44 -07:00
Michael Timothy Grimes bea6b0b5dc Renaming functional tests to include spice exe used. Renaming pex test to separate functional tests from pex test. 2018-09-30 22:39:37 -07:00
Michael Timothy Grimes 6d83ebf50f updating debug messages in functional test 2018-09-30 22:10:11 -07:00
Michael Timothy Grimes 8a56dd2ac9 Finished functional test 2018-09-30 21:20:01 -07:00
Michael Timothy Grimes 26c6232564 Updating functional test. Test can now run a spice simulation and read the dout values from the timing files. 2018-09-28 23:38:48 -07:00
Michael Timothy Grimes a71486e22f Adding mutliport constants to design.py to reduce the need for copied code across multiple modules. 2018-09-28 00:11:39 -07:00
Michael Timothy Grimes 66933ed922 Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-09-27 02:02:24 -07:00
Michael Timothy Grimes 19d68f613e Making changes to bank select for multiport. The height of the nor gate using pbitcell was too short and one of the contacts violated drc. Extended height of nor by drc spacing violation so it could pass in multiport. 2018-09-27 02:01:32 -07:00
Michael Timothy Grimes 1ca0154027 Editting top level netlist for multiport. Now there are multiple control logic modules, one per port. Since diffent ports are driven by different clocks, also separating dff modules, one per port. 2018-09-26 19:10:24 -07:00
Michael Timothy Grimes 648e57d195 Altering bank select for port specific use. Altering bank select test to test different port types. Altering bank for control signal changes. 2018-09-26 14:53:55 -07:00
Michael Timothy Grimes f1560375fc Altering control logic for read ports and write ports, by including only read or write specific circuitry. Altering replica bitline layout to support multiport 2018-09-25 20:00:25 -07:00
Matt Guthaus a7246f5e7f Rename omits 0 size ports 2018-09-24 13:44:31 -07:00
Matt Guthaus 9b0142d6b9 Comment debug for possible performance issue 2018-09-24 11:44:32 -07:00
Matt Guthaus a3f13d6eab Remove banks from test configs 2018-09-24 11:41:51 -07:00
Matt Guthaus 2df9b79b28 Remove scn3me lib files. Remove bank references. 2018-09-24 11:28:43 -07:00
Matt Guthaus 7432192e5e Small change to test webhook 2018-09-24 09:11:44 -07:00
Matt Guthaus 922e3f4c13 Small change to test webhook 2018-09-21 15:05:46 -07:00
Matt Guthaus ade12c9dc2 Small change to test webhook 2018-09-21 15:03:16 -07:00
Matt Guthaus e1864a7a1e Small change to test webhook 2018-09-21 15:02:16 -07:00
Matt Guthaus 2b3b4bbee6 Small change to test webhook 2018-09-21 15:01:07 -07:00
Michael Timothy Grimes 934959952b Corrections to functional test that adds multiple cs_b signals per port 2018-09-21 09:59:44 -07:00
Matt Guthaus 87502374c5 DRC clean supply grid routing on control logic. 2018-09-20 16:00:13 -07:00
Michael Timothy Grimes 2641841e4c Making correction to replica bitline netlist for multiport 2018-09-20 15:21:22 -07:00
Michael Timothy Grimes 938ded3dd6 Adding functional test to characterizer and unit tests in both single and multiport 2018-09-20 15:04:59 -07:00
Michael Timothy Grimes fc5f163828 Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-09-18 18:56:15 -07:00
Matt Guthaus fd9ffe30d6 Add layer width options to route object 
Modify router to use track-width routes.
 2018-09-18 15:12:53 -07:00
Matt Guthaus 8d2804b9cb Supply router working except: 
Off grid pins. Some pins do now span enough of the routing track and must be patched.
  Route track width. Instead of minimum width route, it should be the track width.
 2018-09-18 12:57:39 -07:00
Matt Guthaus bfc8428df7 Convert router tests to scn4m_subm 2018-09-17 13:30:30 -07:00
Matt Guthaus 60cceab50a Merge branch 'dev' into supply_routing 2018-09-17 11:34:31 -07:00
Matt Guthaus a58b1906ad Convert unit tests to scn4m_subm 
Also, fixed isdiff for python3.
 2018-09-17 11:13:46 -07:00
Michael Timothy Grimes 43f5316eed Correcting format of replica_pbitcell. 2018-09-13 18:51:52 -07:00
Michael Timothy Grimes 9acc8a9532 Altering multiport checks across several unit tests. 2018-09-13 18:49:20 -07:00
Michael Timothy Grimes 332976dd73 s_en will be shared amongst the sense amps of different ports, so I'm removing the distinct s_en signals from several modules. 2018-09-13 18:46:43 -07:00
Michael Timothy Grimes 5fd484ee5a Replacing replica_pbitcell module with a more effiecient verision. replica_pbitcell is now a wrapper for pbitcell in replica_bitcell mode. 2018-09-13 16:53:24 -07:00
Matt Guthaus e591176211 Change default to scn4m 2018-09-13 15:26:03 -07:00
Matt Guthaus 93ae7ebd00 Specify DRC,LVS,PEX tool for scn4m 2018-09-13 15:18:30 -07:00
Matt Guthaus 571dca5d5f Hard code flatten commands for the unique id precharge array 2018-09-13 15:15:41 -07:00
Matt Guthaus 4d328c5768 Fix hspice setuphold golden results 2018-09-13 14:41:15 -07:00
Matt Guthaus f4389bdd8f Add extra track spacings in some routes. 2018-09-13 14:12:24 -07:00
Matt Guthaus 63d0523228 Added scn4m_subm. 
Added scn4m_subm files (instead of scn4me_subm).
Fixed missing cifoutput/cifinput in magic tech file and gds files.
Fixed incorrect M3/via3/M4 design rules.
 2018-09-13 12:53:35 -07:00
Matt Guthaus 3539887ee4 Updating ms_flop removal. 
Updated characterizer for dff.
Added new setup/hold results for dff instead of ms_flop.
Removed ms_flop references in sram-base.
Fixed syntax errors in SCN3ME tech file.
 2018-09-13 11:40:24 -07:00
Matt Guthaus 66cbe0966c Removed old ms_flop unit test 2018-09-13 11:15:33 -07:00
Matt Guthaus f8fc7c12b3 Remove ms_flop and replace with dff. Might break setup_hold tests. 2018-09-13 11:02:28 -07:00
Matt Guthaus 849293b95b Converting grid data structures to sets to reduce size. 2018-09-13 09:10:29 -07:00
Michael Timothy Grimes e0b9989d85 Adding replica_pbitcell and test for multi-ported purposes. Altering replica bitline and test to accomodate. 2018-09-13 01:42:06 -07:00
Michael Timothy Grimes f03cd7c3ba Removing multiport_check option that diabled multiport portion of unit tests. Adding multiport checks to several other modules. 2018-09-12 20:22:12 -07:00
Michael Timothy Grimes 42719b8ec2 Fixing netlist_only errors. Removing netlist_only option from ptx because it must always generate layout for pbitcell. gds_write, drc check, and lvs check in local_check() are now in a 'if not OPTS.netlist_only' conditional. These functions will generate errors in netlist_only mode since there is no gds layout to write or check. 2018-09-12 01:53:41 -07:00
Michael Timothy Grimes 7dfd37f79c Altering control logic for multiport. Netlist changes only. 2018-09-12 00:59:07 -07:00
Michael Timothy Grimes bfc855b8b1 Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-09-11 17:33:17 -07:00
Hunter Nichols ac3cc5c79b Merge branch 'dev' into multiport_characterization 2018-09-11 16:01:51 -07:00
Matt Guthaus a3c2b4384a Improve comments. Simplify function interface for channel route. 2018-09-11 15:53:12 -07:00
Hunter Nichols 676b6764c7 Merge branch 'dev' into multiport_characterization 2018-09-11 15:40:17 -07:00
Matt Guthaus 3587f90e94 Fix copy pasta error in create vertical channel route 2018-09-11 14:47:55 -07:00
Matt Guthaus 5e34233479 Finish new VCG testing. 
Reversed VCG graph edge directions.
Channel tracks get added left to right or top down like
normal left edge algorithm examples.
 2018-09-11 14:24:13 -07:00
Matt Guthaus fcc4a75295 Create VCG using nets as nodes rather than pins. 2018-09-11 13:28:28 -07:00
Matt Guthaus add0e3ad68 Add none option for verify wrapper with warning messages. 2018-09-11 10:17:24 -07:00
Hunter Nichols 91bbc556e8 Cleaned up control logic cycle creation in delay.py. Fixed bug which caused input data to be determined by the read ports. 2018-09-10 22:06:50 -07:00
Hunter Nichols da6843af5b Changed power logic in lib file writing. Syntax incorrect still for multiport. To be changed when top-level is done. 2018-09-10 19:33:59 -07:00
Hunter Nichols 5dfa8bc2c6 Fixed known typos of the word transition. 2018-09-10 14:27:26 -07:00
Michael Timothy Grimes 38a1f35ff0 Correcting format of file (removing tabs) 2018-09-10 03:44:08 -07:00
Michael Timothy Grimes a7f03858e8 Adding 'multiport_check' option to OPTS. All of the unit tests that have multiport checks in them are now under this conditional. If you want to remove the multiport drc/lvs checks, you can set the option to False, and it will skip those portions. 2018-09-09 23:25:29 -07:00
Michael Timothy Grimes 5af56e5a3a Adding layout check for sram (1 bank) using pbitcell and 1RW port 2018-09-09 22:45:25 -07:00
Michael Timothy Grimes 0cdd3b99bf Generalized wl names using bitcell's list_all_wl_names function to accomodate multiport 2018-09-09 22:42:52 -07:00
Michael Timothy Grimes 586c72e4f7 Altering certain tests to include multiport checks. 2018-09-09 22:08:03 -07:00
Michael Timothy Grimes 27427d4192 Bank level layout now works with pbitcell and 1RW. Column mux and array have been altered to accomodate multiport. Multiport changes to wordline driver were removed because they were unnecessary. 2018-09-09 22:06:29 -07:00
Michael Timothy Grimes 252ae1effa add trailing 0 to web 2018-09-09 15:16:53 -07:00
Michael Timothy Grimes 68c00d7467 Removing din and dout list names in exchange for a read index. Write ports will always be in order (they will not skip numbers. Read ports however will skip the numbers assigned to wirte ports so the index of the read ports must be tracked. 2018-09-09 14:14:26 -07:00
Michael Timothy Grimes 1429b9ab1a Commiting working version of multi-port that can generate a netlist on the sram level. Changes that will clean up the code are forthcoming. 2018-09-09 14:00:51 -07:00
Michael Timothy Grimes c91735b23b Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-09-08 18:56:58 -07:00
Matt Guthaus 2d86492d91 Working on methodology of blockages, pins, and routing multiple pins. 2018-09-08 18:55:36 -07:00
Matt Guthaus 96c51f3464 Component shape functions. Find connected pins through overlaps. 2018-09-08 10:05:48 -07:00
Hunter Nichols 5cab786e21 Cleaned up analyze and some of its helper functions to be less cluttered. 2018-09-07 17:50:09 -07:00
Matt Guthaus 69261a0dc1 Routing and connecting rails with vias done. 
Refactored grid path class.
Added direction enum.
Does not route multi-track width wires in signal router.
 2018-09-07 14:46:58 -07:00
Hunter Nichols 83f6434476 Gave find_feasible_period a port input. 2018-09-07 00:53:11 -07:00
Hunter Nichols 8aaf1155d1 Fixed test 23_lib_sram_test. Fixed syntax in related golden lib files. 2018-09-06 22:51:34 -07:00
Hunter Nichols 0ff3b29b66 Fixed test 23_sram_prune test. Fixed syntax errors in golden lib files. 2018-09-06 22:06:23 -07:00
Michael Timothy Grimes 1a340c9c85 Merging latest changes from multiport with changes made to pbitcell. Changing select code from other modules and tests to reflect changes made to pbitcell. 2018-09-06 19:36:50 -07:00
Hunter Nichols bf34911f3f Test 21_ngspice now passing for scmos and freepdk45. 21_hspice has leakage power error (but it may be okay) 2018-09-06 18:40:21 -07:00
Hunter Nichols 1615de05e4 Fixed leakage power issue in test 21_hspice. Still requires more testing. 2018-09-06 18:26:08 -07:00
Michael Timothy Grimes 66a8a76fb0 Commiting changes to pbitcell that separate the routing into individual functions and rename. The bitlines and wordlines are also renamed. 2018-09-06 17:59:21 -07:00
Hunter Nichols a2bc82fe71 Fixed test 21_hspice. Leakage power is off. 2018-09-06 17:34:22 -07:00
Hunter Nichols dd22f9acd5 Fixed issues with analytical sram test. Changed syntax errors in golden lib file. 2018-09-06 17:01:10 -07:00
Matt Guthaus c2c17a33d2 Horizontal and vertical grid wires done. 2018-09-06 14:30:59 -07:00
Matt Guthaus cd987479b8 Updates to supply routing. 
Rename astar_grid to signal_grid to parallel supply routing.
Wave expansion for supply rails.
Pin addition for supply rails.
 2018-09-06 11:54:14 -07:00
Hunter Nichols f824d039c6 Merge branch 'dev' into multiport_characterization 2018-09-06 00:25:11 -07:00
Hunter Nichols 66c4782408 Fixed several syntax error regarding some multiport naming. Currently in debug mode. 2018-09-06 00:25:02 -07:00
Hunter Nichols ad235c02c6 Added debug code which skips characterization and goes straight to writing the lib. Fixed some syntax issues in the lib file. 2018-09-05 23:27:13 -07:00
Matt Guthaus 59956f1446 Update signal routing for new blockage and pins. 2018-09-05 16:01:11 -07:00
Matt Guthaus 7ead566154 Remove cell rename during DRC. Keep flatten. 2018-09-05 16:00:48 -07:00
Matt Guthaus b1c63a6c62 Add inflate blockages and remove pins from blockages. 2018-09-05 11:06:17 -07:00
Matt Guthaus 93b24d8c85 Merge remote-tracking branch 'origin/dev' into supply_routing 2018-09-05 11:05:41 -07:00
Matt Guthaus ba651d53ae Change options in pbitcell test to be global again. 2018-09-05 10:59:41 -07:00
Matt Guthaus 2a27fbc98e Fix temp directory preservation option. 
Make labels in freepdk45 replica bitcell lower case.
 2018-09-05 10:02:12 -07:00
Matt Guthaus 0f87ba742f Add back LEF blockages. Remove "absolute" flags from GDS output 2018-09-05 09:28:43 -07:00
Matt Guthaus 8ffdcdf277 Fixed bit shift amount error. Removed rotate flag for Calibre. 2018-09-04 17:27:50 -07:00
Matt Guthaus 5395f21be9 Remove unique id in contact that was used for debugging 2018-09-04 16:40:52 -07:00
Matt Guthaus 9d40cd4a03 Remove verbose print statement in add_power_pin 2018-09-04 16:39:13 -07:00
Matt Guthaus 378993ca22 Found rotate bug in transformCoordinate. Cleaned up transFlags. 2018-09-04 16:35:40 -07:00
Matt Guthaus 763f1e8dee Finish renaming replica bitcell and bitline pin names. 2018-09-04 14:03:15 -07:00
Matt Guthaus 6963a1092f Make bitcell width/height not static. Update modules to use it for pbitcell. 2018-09-04 11:55:22 -07:00
Matt Guthaus 0adfe66429 Add total_ port variables to sram base class. 2018-09-04 11:15:18 -07:00
Matt Guthaus de6f22aa3c Fix unit test permissions 2018-09-04 10:48:37 -07:00
Matt Guthaus 19c0e1638b Merge remote-tracking branch 'origin/multiport' into multiport 2018-09-04 10:47:55 -07:00
Matt Guthaus a346bddd88 Cleanup some items with new sram_config. Update unit tests accordingly. 2018-09-04 10:47:24 -07:00
Hunter Nichols 3bde83bdbe Added initial structure changes to lib. Crashes when writing to lib file. 2018-09-04 00:43:44 -07:00
Michael Timothy Grimes af0756382f Merging changes and updating multiport syntax across several tests 2018-09-03 19:36:20 -07:00
Michael Timothy Grimes 774c14ad75 changing 19_psingle_bank_test to test layout for a single bank using pbitcell with 1 RW port (equivalent to using 6T cell) 2018-09-03 17:47:29 -07:00
Michael Timothy Grimes 341a3ee68d Adding multiport pin names to sram_base for netlist only use 2018-09-03 17:44:32 -07:00
Michael Timothy Grimes 1e5924d1b7 Adding multiported bank_sel pins 2018-09-03 17:35:00 -07:00
Michael Timothy Grimes d3441c7ba4 Altering wordline driver to size for any bitcell. Editting multi-port test cases for sense amp array, write driver array, and wordline driver to least number of ports as a better test of spacing betwwen amps/drivers 2018-09-03 17:31:12 -07:00
Hunter Nichols 1af5bb3758 Remove code bloat and simplified port logic in some cases. Crashes while writing to lib. 2018-09-01 00:10:40 -07:00
Michael Timothy Grimes f3cca7eea0 Altering sense amp array and write driver array so spacing between amps/drivers accomodates multiport. Also altering sense amp array and write driver array tests to include multiport cases. 2018-08-31 23:28:06 -07:00
Matt Guthaus 9d8d2b65e4 Fix delay test with new sram_config. Merge dev changes. 2018-08-31 13:01:17 -07:00
Matt Guthaus c3bd54696f Merge branch 'dev' into multiport 2018-08-31 12:56:25 -07:00
Matt Guthaus 563ff77d44 Add sram_config class. Rename port variables for better description. 2018-08-31 12:03:28 -07:00
Michael Timothy Grimes 75d77095d0 merging changes to magic.py 2018-08-31 09:01:15 -07:00
Hunter Nichols 4022f014b2 Merge branch 'dev' into multiport_characterization 2018-08-31 00:43:33 -07:00
Hunter Nichols 60088c2dfb Added changes to lib to allow the default to run. Will crash with multiport options. 2018-08-31 00:42:56 -07:00
Hunter Nichols 6614c3eb51 Altered min_period algorithm to work for multiport. Works for default config but mostly untested for multiport options. 2018-08-30 22:43:56 -07:00
Hunter Nichols 5989a3c952 Expanded run_delay_stimulas to multiport. Bug Fixes as well. 2018-08-30 17:08:34 -07:00
Hunter Nichols 907b7310ee Actually changed the noops default data in this commit. 2018-08-30 15:16:54 -07:00
Hunter Nichols 53fa6108e1 Changed most noops calls to have default input of all 0's. Changed parse_values to return dict even if some values fail. 2018-08-30 15:11:54 -07:00
Matt Guthaus 3ab0b569cb Use a .magicrc in the technology directory to read magic tech files 2018-08-30 14:20:41 -07:00
Michael Timothy Grimes 35ae4a275e Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-08-30 12:42:24 -07:00
Hunter Nichols 73388e9797 Merge branch 'dev' into multiport_characterization 2018-08-30 01:20:23 -07:00
Hunter Nichols e32c1fdd23 Changed part (4) of analyze to use the updated measure names. 2018-08-30 01:18:34 -07:00
Hunter Nichols 78be724867 Edited find_feasible period to use dynamic naming on its measured values and edited the algorithm to work with multiport. 2018-08-30 00:11:14 -07:00
Hunter Nichols 02cf51d3be Added generic parsing function to capture multiple values. This commit does not run and it messes up some naming conventions 2018-08-29 22:16:42 -07:00
Matt Guthaus 762f2d894c Revert all transFlags in GdsMill 2018-08-29 17:23:04 -07:00
Matt Guthaus 93a6247f26 Unrotate vias in delay chain 2018-08-29 17:21:53 -07:00
Hunter Nichols 4b515fe1ac Changed create_test_cycles to have targeted ports for characterization rather than all ports always. 2018-08-29 17:16:11 -07:00
Michael Timothy Grimes e118cc2d5c Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-08-29 16:06:50 -07:00
Michael Timothy Grimes aeaab13d28 Unit tests for pbitcell now passing, so commenting out skip line. Also gave pbitcell_array useful names in unit test for easier debugging 2018-08-29 16:05:13 -07:00
Matt Guthaus 5a065cf701 Remove setting of rotate transflag. Not supported in Calibre? 2018-08-29 16:04:15 -07:00
Michael Timothy Grimes 7ef7c084cd fixed typo that added two '/' characters to path sys command (i.e. from tech//SCN3ME_SUBM.30 to tech/SCN3ME_SUBM.30) 2018-08-29 16:01:25 -07:00
Michael Timothy Grimes 29da8a5209 Further changes to pbitcell so that it passes unit tests for bitcell_array 2018-08-29 15:54:49 -07:00
Matt Guthaus 334aa53cee Merge branch 'supply_routing' of https://github.com/VLSIDA/PrivateRAM into supply_routing 2018-08-29 15:40:04 -07:00
Matt Guthaus 73289a6090 Clean up GdsMill. Fix rotate bug I introduced in transFlags! 2018-08-29 15:34:45 -07:00
Matt Guthaus 0ce2dd2791 Add supply_grid file 2018-08-29 15:34:45 -07:00
Matt Guthaus 27bb1d2ee7 Rewrite blockage routines in router. Clean up GdsMill code. 2018-08-29 15:34:45 -07:00
Matt Guthaus 04b7c419f1 Rename _new cell back to original for LVS comparison script 2018-08-29 15:34:45 -07:00
Matt Guthaus 5386b7a0f4 Initial refactor of signal and supply router classes. 2018-08-29 15:34:45 -07:00
Matt Guthaus 19d14e39ce Remove extraneous files 2018-08-29 15:34:45 -07:00
Matt Guthaus 6220ea6d47 Update router to work with pin_layout structure. 2018-08-29 15:34:45 -07:00
Matt Guthaus 41fba9d27c Add sketch for power grid routing code 2018-08-29 15:34:16 -07:00
Michael Timothy Grimes 807a4d7767 Fixed drcs error in magic. Pbitcell should now pass unit tests in calibre and magic. 2018-08-29 15:30:50 -07:00
Hunter Nichols 775fe7b57c Fixed measure statement stating times. This commit crashes if there are no readwrite ports. 2018-08-29 15:13:31 -07:00
Michael Timothy Grimes 1d5a41df2d fixed issue with read ports that caused extra transistors to appear 2018-08-29 08:52:45 -07:00
Hunter Nichols 8a0411279e Merge branch 'dev' into multiport_characterization 2018-08-29 01:27:37 -07:00
Hunter Nichols 8fad81ff1e Changed delay measures to add additional measure based on # of ports. Measure times are not correct yet. 2018-08-29 00:43:27 -07:00
Hunter Nichols ffe59bdf51 Edited delay measures to handle multiple readwrite ports. This commit is not well tested. 2018-08-29 00:01:22 -07:00
Matt Guthaus e804f36bec Add parameters to give preference to DRC/LVS/PEX tools like we do for spice. 2018-08-28 13:41:26 -07:00
Hunter Nichols fa8434e5f0 Added debug checks for unsupported port options. 2018-08-28 13:01:35 -07:00
Hunter Nichols bd763fa1e3 Fixed naming issue between sram instance and PWL in stimulus 2018-08-28 12:09:02 -07:00
Matt Guthaus 309bfaea2a Update comments in magic to download the correct version of design rules 2018-08-28 11:48:23 -07:00
Matt Guthaus 8752d799b4 Skip pbitcell tests for now 2018-08-28 10:45:50 -07:00
Matt Guthaus 95a8688506 Rewrite blockage routines in router. Clean up GdsMill code. 2018-08-28 10:43:45 -07:00
Matt Guthaus 0dbc88dab2 Rename _new cell back to original for LVS comparison script 2018-08-28 10:43:44 -07:00
Matt Guthaus 82833ef8f0 Initial refactor of signal and supply router classes. 2018-08-28 10:43:44 -07:00
Matt Guthaus 8f1e2675fe Remove extraneous files 2018-08-28 10:43:44 -07:00
Matt Guthaus 2ae1e0234d Update router to work with pin_layout structure. 2018-08-28 10:43:44 -07:00
Matt Guthaus ea52af3747 Add sketch for power grid routing code 2018-08-28 10:43:44 -07:00
Matt Guthaus ac8a16ebdf Fix permissions for unit tests to be run standalone. 2018-08-28 10:31:58 -07:00
Matt Guthaus e17c69be3e Clean up new code for add_modules, add_pins and netlist/layouts. 2018-08-28 10:24:09 -07:00
Hunter Nichols 0bb4b48439 Merge branch 'dev' into multiport_characterization 2018-08-28 00:37:26 -07:00
Hunter Nichols 75da5a994b Edited create_test_cycles to generate values that characterize all ports. Still several bugs and lib file does not support multiple ports. 2018-08-28 00:30:15 -07:00
Hunter Nichols ba5988ec7f Added write port structure to create_test_cycles. This commit contains test code. 2018-08-27 20:35:29 -07:00
Hunter Nichols d82d3df4a7 Added read port cycle data generation. This commit contains test code in create_test_cycles 2018-08-27 18:17:02 -07:00
Matt Guthaus 6401cbf2a6 Move place function to instance class rather than hierarchy. 2018-08-27 17:25:39 -07:00
Matt Guthaus 8664f7a0b8 Converted all modules to not run create_layout when netlist_only 
mode is enabled.
 2018-08-27 16:42:48 -07:00
Hunter Nichols a0e06809f9 Comments now display port in stim file. 2018-08-27 16:23:23 -07:00
Hunter Nichols 350823d434 Added basic structure to add_test_cycles to characterize multiple ports and its helper functions to allow for ports to be selected for characterization 2018-08-27 15:56:42 -07:00
Matt Guthaus 9f051df18d Added netlist only configuration option. 2018-08-27 14:33:02 -07:00
Matt Guthaus 19d46f5954 Finalized separation of netlist/layout creation. 2018-08-27 14:18:32 -07:00
Matt Guthaus 0daad338e4 All modules have split netlist/layout. 2018-08-27 11:13:34 -07:00
Matt Guthaus 87f539f3a8 Separate netlist/layout for flop and precharge array. 2018-08-27 10:54:21 -07:00
Matt Guthaus 138a70fc23 Add place_inst routine. 
Separate create netlist and layout in some modules.
 2018-08-27 10:42:40 -07:00
Michael Timothy Grimes 8c73a26daa Changing function names in bitcell and pbitcell to better reflect what values they're returning. Editting function calls in bitcell_array and bank accordingly. 2018-08-26 14:37:17 -07:00
Hunter Nichols 6dc72f5b1e Added additional control signal to stim file based on # of ports. 2018-08-23 17:46:24 -07:00
Hunter Nichols efcb435fde Changed # of address signals to reflect # of ports in delay 2018-08-23 14:49:56 -07:00
Hunter Nichols 9151858449 Characterizer now recognizesmultiple ports and additional DIN/DOUT signals are added to stim file. 2018-08-22 23:45:43 -07:00
Hunter Nichols 21e85297d3 Merge branch 'dev' into multiport_characterization 2018-08-22 14:50:29 -07:00
Hunter Nichols 8abf45a5d3 Some test code added. To be removed later. 2018-08-22 14:19:09 -07:00
Michael Timothy Grimes b8ae21a52b made multi-port changes to sram. This commit will allow all levels of openram to pass unit tests 2018-08-20 22:11:24 -07:00
Michael Timothy Grimes f0cca8293c Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-08-19 00:01:52 -07:00
Michael Timothy Grimes 8e3dc332f3 changed control signal names in bank select to accommodate multi-port changes in bank 2018-08-19 00:00:42 -07:00
Michael Timothy Grimes 19ca0d6c2a Changing control logic names to match naming scheme for multi-port. din[0] to din0[0], s_en to s_en0, addr[0] to addr0[0], etc. Sram level should pass unit tests for single port but will not currently pass for multi-port 2018-08-18 16:51:21 -07:00
Michael Timothy Grimes 0f8da1510e Reverting pin name changes of precharge cell and array back to 'bl' and 'br'. Also clarifying bl and br init parameters to reflect that they refer to the bitcell lines. 2018-08-18 15:27:07 -07:00
Matt Guthaus e3f2ee8a7e Fix VCG error in channel route. 
Note, the channel routing algorithm still does not handle
horizontal conflicts or cyclic vertical conflicts!
 2018-08-15 14:19:04 -07:00
Matt Guthaus 6e332e581a Updated to include local magic rules 2018-08-15 09:46:23 -07:00
Michael Timothy Grimes e147f807a5 adding a unit test for multiported bank, this test will skip in the regression testing because multiported bank does not pass drc yet 2018-08-15 04:32:56 -07:00
Michael Timothy Grimes e4a94e8597 Merging changes to bank. Bank has been altered to accommodate multiport. Single port still passes unit test, though some control signal names have been changed to have a following 0 (e.g. s_en to s_en0). Multiport does not pass drc yet, but can accurately generate a spice netlist. 2018-08-15 04:00:48 -07:00
Michael Timothy Grimes e592d95146 Altered bank to accommodate multiport. Single port still works, though some of the control signal names have been changes to have a following 0 (e.g. s_en to s_en0). Multiport does not pass drc yet, but can generate an accurate spice netlist. 2018-08-15 03:36:40 -07:00
Michael Timothy Grimes a5af4a2b9c resolved variable name error in 00_code_format test 2018-08-15 03:33:33 -07:00
Michael Timothy Grimes af43fb6276 called bitcell function before reading the height of the bitcell because pbitcell's dynamic height can only be determined after the module is called 2018-08-15 02:19:36 -07:00
Michael Timothy Grimes 040340b49f editted naming convention on precharge to accommodate multiport 2018-08-15 02:14:45 -07:00
Michael Timothy Grimes 8d97862f6e altered precharge array and precharge unit tests to accommodate multiport 2018-08-15 00:55:23 -07:00
Matt Guthaus 36bfd2932a Update delay results with new clock routing 2018-08-14 10:51:02 -07:00
Matt Guthaus 8900edbe12 Finalize single bank clock routing. 2018-08-14 10:36:35 -07:00
Matt Guthaus 3420b1002c Connect data and column DFF clocks in 1 bank. 2018-08-14 10:09:41 -07:00
Matt Guthaus 5ff49d322d bank_sel_bar only used for clk now 2018-08-13 15:14:52 -07:00
Matt Guthaus f7f318d72e Remove tri_en signals from bank control logic. 2018-08-13 14:47:03 -07:00
Matt Guthaus 49bee6a96e Remove OEB signal since we split DIN/DOUT ports 2018-08-13 14:09:49 -07:00
Matt Guthaus 9ffba4b052 Add +x permissions on precharge and pbitcell tests 2018-08-13 09:57:10 -07:00
Matt Guthaus 34736b7b3f Remove carriage returns form python files 2018-08-07 09:44:01 -07:00
Matt Guthaus abacf6a2d0 Add carriage return check for python files 2018-08-07 09:40:45 -07:00
Michael Timothy Grimes c2a9e91dba Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-08-05 19:53:28 -07:00
Michael Timothy Grimes 5666ee6635 altered precharge module to accomodate bitlines from pbitcell, and altered unit test to test both bitcell and pbitcell configurations 2018-08-05 19:46:05 -07:00
Michael Timothy Grimes ecd4612167 altered bitcell, pbitcell, and bitcell array modules to accomodate additional bitline reference functions 2018-08-05 19:43:59 -07:00
Matt Guthaus c0d5f781cf Not sure how VCG channel constraint got removed. Fixed this bug before... 2018-07-27 15:15:40 -07:00
Matt Guthaus a7a3099702 Fix comments in stimulus file to show list and not zip type 2018-07-27 15:00:00 -07:00
Matt Guthaus d739c17b8d Fix delay numbers in hspice delay unit test. 2018-07-27 14:43:52 -07:00
Matt Guthaus d75d17bc8a Update golden results for FreePDK45 tests. 2018-07-27 14:25:52 -07:00
Matt Guthaus 642a5cfe73 Line-wrap pinv debug formatting 2018-07-27 14:07:55 -07:00
Matt Guthaus 71606e1097 Add read cycle to clear DOUT bus before each read measure. 2018-07-27 14:06:59 -07:00
Matt Guthaus 8f72621f4a Converted delay measurement to use add_read/add_write functions. 
Rewrote the logic to add one cycle at a time for easier
manipulation. This can be extended more easily into the
functional simulations.
 2018-07-27 11:36:17 -07:00
Matt Guthaus 5b2cb6a95e Update remaining SCMOS golden lib files. 2018-07-27 09:44:12 -07:00
Matt Guthaus 6b967c08dd Updated output messages in timing test comparisons. 
Added output to show which lines differ and what their line numbers are..
Added output to show relative difference of approximate compares.
Added output to include file names that mismatch.
 2018-07-27 09:34:44 -07:00
Matt Guthaus 01cbc71a2a Limit sizes for dff_buf too. Add comments about restriction. 2018-07-27 08:17:50 -07:00
Matt Guthaus b541efe959 Fix wide gnd rail spacing to inverter NMOS by adding size limit to pinv. 2018-07-27 07:23:18 -07:00
Matt Guthaus 0e0516c4a6 Fix delay test unit test results. 2018-07-26 16:45:09 -07:00
Matt Guthaus 85595b0f6f Update format of delay test output during an error to directly 
copy into unit test. Factor function into testutils.py for comparison.
 2018-07-26 16:05:24 -07:00
Matt Guthaus 5088487cf7 Update delay tests to output useful information for debug. 2018-07-26 15:45:17 -07:00
Matt Guthaus a00e160274 Convert bitline index to integer in trim_spice 2018-07-26 14:29:44 -07:00
Matt Guthaus f098b995f0 Fix pinvbuf test to use new interface with only driver size. 2018-07-26 14:20:00 -07:00
Matt Guthaus c8808c268a Close output log in test 30 to avoid warning 2018-07-26 14:01:40 -07:00
Matt Guthaus bc67ad5ead Fixed timing to be measured from positive clock edge since 
reading a 1 will be the precharge time.
Started modifying the lib file for DIN and DOUT ports, but did not
check the syntax yet.
 2018-07-26 13:58:50 -07:00
Matt Guthaus e827c1b8c7 Make pinvbuf have unique names for GDS compliance. 
Add back gating of w_en since write should happen in second half
or else we will have write and precharge simultaneously active.
 2018-07-26 11:40:40 -07:00
Matt Guthaus 00a87d57ab Modified pinvbuf to have a stage effort of 4 for driving the 
clock bar to wordline enable.
Fixed comments in stimulus file to have right cycle numbers.
Removed clock gating on we signal since clock gating is already
done on the WL signals. It is redundant.
 2018-07-26 11:28:48 -07:00
Michael Timothy Grimes fb0de710ec Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-07-26 09:04:59 -07:00
Michael Timothy Grimes 27ab411146 fixed error I missed in pbitcell_array test 2018-07-26 09:02:52 -07:00
Matt Guthaus dd7069dd98 Remove print statement 2018-07-25 15:51:48 -07:00
Matt Guthaus b7525a14c2 Change DIN to DOUT in characterizer. Spacing dff flops down by m2 not m1 pitch. 2018-07-25 15:50:49 -07:00
Matt Guthaus d6df215718 Always use m2_pitch as default for channel for via spacing rules 2018-07-25 15:47:11 -07:00
Matt Guthaus 6d71c3f790 Fix bug to remove pin from conflicts in addition to graph keys 2018-07-25 15:36:16 -07:00
Matt Guthaus a4bfbe3545 Move dff_array pins to center of rail 2018-07-25 15:08:04 -07:00
Matt Guthaus 44f0e4a1de Fix new offset coordinate syntax error 2018-07-25 13:47:36 -07:00
Matt Guthaus 64b3cfee26 Only print LVS/DRC stats when it is enabled 2018-07-25 13:44:34 -07:00
Matt Guthaus 7c254d540d Change channel route api to use pin maps instead of an insteads for cases where there are multiple instances that have the pins (e.g. decoders) 2018-07-25 11:37:06 -07:00
Matt Guthaus f7a2766c29 First draft of naive channel route in hierarchy_layout. It doesn't implement horizontal conflicts or try to minimize the number of channels. 2018-07-25 11:13:30 -07:00
Matt Guthaus 48d3b25b74 Rotate the output pins of the control logic. Need to fix this permanently. 2018-07-24 14:26:01 -07:00
Matt Guthaus 16a084fde1 Add vdd/gnd at right end of rails. Rename some signals for clarity. 2018-07-24 14:15:11 -07:00
Matt Guthaus aa2ea26db3 Convert control module to use hierarchy bus API 2018-07-24 10:35:07 -07:00
Matt Guthaus b50f57ea3a Remove control logic supply rails and replace with M3 supply pins 2018-07-24 10:12:54 -07:00
Matt Guthaus 45a53ed089 Rotate via in center for freepdk 2018-07-19 14:01:48 -07:00
Matt Guthaus 4c3bd0e42b Move WL gnd contacts outside the cell for simplicity 2018-07-19 13:38:45 -07:00
Matt Guthaus beee8229d1 Revert change. Add gnd pin to right on bitline load. 2018-07-19 13:26:12 -07:00
Matt Guthaus ea53066966 Align RBL inverter with first load inverter in delay chain to aid supply connections 2018-07-19 11:02:13 -07:00
Matt Guthaus 311ab97bfc Fix s_en stages to be even per Kevin's bug report. Assert minimum fanout to ensure vdd/gnd connections. 2018-07-19 10:51:20 -07:00
Matt Guthaus 128dfd5830 Add internal vdd/gnd connections for delay chain 2018-07-19 10:37:47 -07:00
Matt Guthaus 51958814a0 Fixing power via problems in freepdk45 2018-07-19 10:23:08 -07:00
Matt Guthaus 9983408fa3 Add verilog_write to sram wrapper for verilog unit test 2018-07-19 10:05:30 -07:00
Matt Guthaus 3f57853969 Use lower case names except for leaf cells and top level 2018-07-18 15:10:57 -07:00
Matt Guthaus 4a139b682d Add temporary options to LVS to allow name merging 2018-07-18 15:10:29 -07:00
Matt Guthaus a9c0ec5549 Add LVS correspondence points to each bank type 2018-07-18 14:29:04 -07:00
Matt Guthaus a878ce5500 Standardize DRC and LVS message levels 2018-07-18 14:28:43 -07:00
Matt Guthaus 58896a6f8e Fix control signal names on control_logic input 2018-07-18 13:41:44 -07:00
Matt Guthaus b88947ef5c Pass the sram design to lib instead of the sram wrapper 2018-07-18 11:51:42 -07:00
Matt Guthaus f43d4cc98f Fix routing clk connections of dff arrays 2018-07-18 11:38:58 -07:00
Matt Guthaus 0701fceb0b Use sram rather than new meta-sram class in the characterizer for delay 2018-07-18 10:39:29 -07:00
Matt Guthaus 1130062343 Fix syntax error in delay test to use new sram wrapper module 2018-07-18 10:33:18 -07:00
Matt Guthaus b8a3bc9b1a Space hier decoder input connections along rails to avoid conflicts 2018-07-18 10:21:58 -07:00
Matt Guthaus b8e3629923 Fix syntax error in unit test 2018-07-17 15:14:22 -07:00
Matt Guthaus 01655b1d54 Clean up tests. Enable 8-way tests. Some tests still have channel route conflicts. 2018-07-17 15:13:00 -07:00
Matt Guthaus ef60b02a81 Add vdd/gnd pins to dff_array 2018-07-17 15:01:31 -07:00
Matt Guthaus 6133d54684 Fix spacing between adjacent decoders 2018-07-17 15:01:16 -07:00
Matt Guthaus ffc866ef78 Single bank working except for channel routing error in 4-way case. 2018-07-17 14:40:04 -07:00
Matt Guthaus 7a69fc1bca Add col addr routing and data routing 2018-07-17 14:24:44 -07:00
Matt Guthaus 0665d51249 Must connect clock at top level for now 2018-07-17 14:24:07 -07:00
Matt Guthaus e82f97cce1 Add create_bus and connect_bus api 2018-07-17 14:23:29 -07:00
Matt Guthaus 0175c88a16 Convert predecodes to use create_bus api 2018-07-17 14:23:06 -07:00
Matt Guthaus ac22b1145f Convert bank to use create_bus routines. 
Modify control logic to have correct offset in SRAM.
 2018-07-16 14:13:41 -07:00
Matt Guthaus 77e786ae5e Fix bug in recomputing boundary with a new offset 2018-07-16 13:46:12 -07:00
Matt Guthaus afcc3563ae Add new supplies to RBL and control logic 2018-07-16 12:58:15 -07:00
Matt Guthaus 93e830e800 Add new supplies to replica bitline 2018-07-16 10:49:43 -07:00
Matt Guthaus 3bbb604504 Add new power supplies to delay chain 2018-07-16 10:19:52 -07:00
Matt Guthaus f3ae29fe0b Getting single bank to work reliably. Removed tri_gate from bank 
for now. Will add it in multibank arrays only. Not needed for
separate DIN and DOUT ports.
 2018-07-13 14:45:46 -07:00
Matt Guthaus 834fbac8de Remove extra print statements. 
Add wrappers for file generation in sram wrapper class.
 2018-07-13 09:38:43 -07:00
Matt Guthaus 0c23efe49b Reference local sram instance in sram.py. 2018-07-13 09:30:14 -07:00
Michael Timothy Grimes 2388ddbfb0 deleting code added in error to pbitcell_array_test during previous commit 2018-07-12 23:55:54 -07:00