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Made global names for pins types. Fixed bugs in tests.

This commit is contained in:
Hunter Nichols 2018-09-19 00:25:27 -07:00
parent d2120d6910
commit 65edc70cfd
3 changed files with 34 additions and 23 deletions
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33
compiler/characterizer/delay.py
View File

@ -51,21 +51,32 @@ class delay():
#Only used to instantiate SRAM in stim file. TODO, extend to every function in this file.
self.create_pin_names()
#Create global measure names. May be an input at some point.
#Create global measure names. Should maybe be an input at some point.
self.create_measurement_names()
def create_measurement_names(self):
"""Create measurement names. The names themselves currently define the type of measurement"""
#Altering the names will crash the characterizer. TODO: object orientated approach to the measurements.
self.delay_meas_names = ["delay_lh", "delay_hl", "slew_lh", "slew_hl"]
self.power_meas_names = ["read0_power", "read1_power", "write0_power", "write1_power"]
def create_pin_names(self):
"""Creates the pins names of the SRAM based on the no. of ports"""
self.pin_names = []
self.address_name = "A"
self.inp_data_name = "DIN"
self.out_data_name = "DOUT"
#This is TODO once multiport control has been finalized.
#self.control_name = "CSB"
for write_input in self.write_ports:
for i in range(self.word_size):
self.pin_names.append("DIN{0}[{1}]".format(write_input, i))
self.pin_names.append("{0}{1}[{2}]".format(self.inp_data_name,write_input, i))
for port in range(self.total_port_num):
for i in range(self.addr_size):
self.pin_names.append("A{0}[{1}]".format(port,i))
self.pin_names.append("{0}{1}[{2}]".format(self.address_name,port,i))
#These control signals assume 6t sram i.e. a single readwrite port. If multiple readwrite ports are used then add more
#control signals. Not sure if this is correct, consider a temporary change until control signals for multiport are finalized.
@ -77,7 +88,7 @@ class delay():
self.pin_names.append("{0}".format(tech.spice["clk"]))
for read_output in self.read_ports:
for i in range(self.word_size):
self.pin_names.append("DOUT{0}[{1}]".format(read_output, i))
self.pin_names.append("{0}{1}[{2}]".format(self.out_data_name,read_output, i))
self.pin_names.append("{0}".format(tech.spice["vdd_name"]))
self.pin_names.append("{0}".format(tech.spice["gnd_name"]))
@ -151,7 +162,7 @@ class delay():
self.sf.write("\n* SRAM output loads\n")
for port in self.read_ports:
for i in range(self.word_size):
self.sf.write("CD{0}{1} DOUT{0}[{1}] 0 {2}f\n".format(port,i,self.load))
self.sf.write("CD{0}{1} {2}{0}[{1}] 0 {3}f\n".format(port,i,self.out_data_name,self.load))
def write_delay_stimulus(self):
@ -230,11 +241,11 @@ class delay():
self.sf.write("\n* Generation of data and address signals\n")
for write_port in self.write_ports:
for i in range(self.word_size):
self.stim.gen_constant(sig_name="DIN{0}[{1}] ".format(write_port, i),
self.stim.gen_constant(sig_name="{0}{1}[{2}] ".format(self.inp_data_name,write_port, i),
v_val=0)
for port in range(self.total_port_num):
for i in range(self.addr_size):
self.stim.gen_constant(sig_name="A{0}[{1}]".format(port, i),
self.stim.gen_constant(sig_name="{0}{1}[{2}]".format(self.address_name,port, i),
v_val=0)
# generate control signals
@ -259,7 +270,7 @@ class delay():
debug.check('lh' in delay_name or 'hl' in delay_name, "Measure command {0} does not contain direction (lh/hl)")
trig_clk_name = "clk"
meas_name="{0}{1}".format(delay_name, port)
targ_name = "{0}".format("DOUT{0}[{1}]".format(port,self.probe_data))
targ_name = "{0}".format("{0}{1}[{2}]".format(self.out_data_name,port,self.probe_data))
half_vdd = 0.5 * self.vdd_voltage
trig_slew_low = 0.1 * self.vdd_voltage
targ_slew_high = 0.9 * self.vdd_voltage
@ -1034,7 +1045,7 @@ class delay():
""" Generates the PWL data inputs for a simulation timing test. """
for write_port in self.write_ports:
for i in range(self.word_size):
sig_name="DIN{0}[{1}] ".format(write_port, i)
sig_name="{0}{1}[{2}] ".format(self.inp_data_name,write_port, i)
self.stim.gen_pwl(sig_name, self.cycle_times, self.data_values[write_port][i], self.period, self.slew, 0.05)
def gen_addr(self):
@ -1044,7 +1055,7 @@ class delay():
"""
for port in range(self.total_port_num):
for i in range(self.addr_size):
sig_name = "A{0}[{1}]".format(port,i)
sig_name = "{0}{1}[{2}]".format(self.address_name,port,i)
self.stim.gen_pwl(sig_name, self.cycle_times, self.addr_values[port][i], self.period, self.slew, 0.05)
def gen_control(self):

12
compiler/tests/21_hspice_delay_test.py
View File

@ -58,12 +58,12 @@ class timing_sram_test(openram_test):
'delay_lh': [0.2255964],
'leakage_power': 0.0019498999999999996,
'min_period': 4.844,
'read0_power0': [0.055371399999999994],
'read1_power0': [0.0520225],
'slew_hl0': [0.0794261],
'slew_lh0': [0.0236264],
'write0_power0': [0.06545659999999999],
'write1_power0': [0.057846299999999996]}
'read0_power': [0.055371399999999994],
'read1_power': [0.0520225],
'slew_hl': [0.0794261],
'slew_lh': [0.0236264],
'write0_power': [0.06545659999999999],
'write1_power': [0.057846299999999996]}
elif OPTS.tech_name == "scn4m_subm":
golden_data = {'delay_hl': [3.452],
'delay_lh': [1.3792000000000002],

12
compiler/tests/21_ngspice_delay_test.py
View File

@ -57,12 +57,12 @@ class timing_sram_test(openram_test):
'delay_lh': [0.22870469999999998],
'leakage_power': 0.0009567935,
'min_period': 4.844,
'read0_power0': [0.0547588],
'read1_power0': [0.051159970000000006],
'slew_hl0': [0.08164099999999999],
'slew_lh0': [0.025474979999999998],
'write0_power0': [0.06513271999999999],
'write1_power0': [0.058057000000000004]}
'read0_power': [0.0547588],
'read1_power': [0.051159970000000006],
'slew_hl': [0.08164099999999999],
'slew_lh': [0.025474979999999998],
'write0_power': [0.06513271999999999],
'write1_power': [0.058057000000000004]}
elif OPTS.tech_name == "scn4m_subm":
golden_data = {'delay_hl': [3.644147],
'delay_lh': [1.629815],