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Further changes to pbitcell so that it passes unit tests for bitcell_array

This commit is contained in:
Michael Timothy Grimes 2018-08-29 15:54:49 -07:00
parent 807a4d7767
commit 29da8a5209
1 changed files with 2 additions and 2 deletions
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4
compiler/pgates/pbitcell.py
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@ -242,7 +242,7 @@ class pbitcell(pgate.pgate):
- self.read_port_flag*self.write_to_read_spacing \
- self.read_port_flag*(self.read_nmos.active_height + (self.num_read-1)*self.read_tile_width) \
- end_connection \
- 0.5*drc["minwidth_metal2"]
- 0.5*drc["poly_to_polycontact"]
self.rightmost_xpos = -self.leftmost_xpos
@ -259,7 +259,7 @@ class pbitcell(pgate.pgate):
+ self.rail_tile_height
# calculations for the cell dimensions
array_vdd_overlap = 0.5*drc["minwidth_metal1"]
array_vdd_overlap = 0.5*contact.well.width
self.width = -2*self.leftmost_xpos
self.height = self.topmost_ypos - self.botmost_ypos - array_vdd_overlap