mirror of https://github.com/VLSIDA/OpenRAM.git
Cleaned up indexing in variable that records cycle times.
This commit is contained in:
Hunter Nichols
parent
3ac2d29940
commit
f30e54f33c
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@ -155,9 +155,6 @@ class delay(simulation):
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"""
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self.check_arguments()
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# obtains list of time-points for each rising clk edge
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#self.create_test_cycles()
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# creates and opens stimulus file for writing
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temp_stim = "{0}/stim.sp".format(OPTS.openram_temp)
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self.sf = open(temp_stim, "w")
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@ -217,10 +214,10 @@ class delay(simulation):
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trig_name = trig_clk_name
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if 'lh' in delay_name:
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targ_dir="RISE"
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trig_td = targ_td = self.cycle_times[self.measure_cycles["read1_{0}".format(port)]]
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trig_td = targ_td = self.cycle_times[self.measure_cycles[port]["read1"]]
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else:
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targ_dir="FALL"
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trig_td = targ_td = self.cycle_times[self.measure_cycles["read0_{0}".format(port)]]
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trig_td = targ_td = self.cycle_times[self.measure_cycles[port]["read0"]]
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elif 'slew' in delay_name:
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trig_name = targ_name
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@ -228,12 +225,12 @@ class delay(simulation):
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trig_val = trig_slew_low
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targ_val = targ_slew_high
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targ_dir = trig_dir = "RISE"
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trig_td = targ_td = self.cycle_times[self.measure_cycles["read1_{0}".format(port)]]
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trig_td = targ_td = self.cycle_times[self.measure_cycles[port]["read1"]]
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else:
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trig_val = targ_slew_high
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targ_val = trig_slew_low
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targ_dir = trig_dir = "FALL"
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trig_td = targ_td = self.cycle_times[self.measure_cycles["read0_{0}".format(port)]]
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trig_td = targ_td = self.cycle_times[self.measure_cycles[port]["read0"]]
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else:
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debug.error(1, "Measure command {0} not recognized".format(delay_name))
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return (meas_name,trig_name,targ_name,trig_val,targ_val,trig_dir,targ_dir,trig_td,targ_td)
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@ -254,11 +251,11 @@ class delay(simulation):
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#Different naming schemes are used for the measure cycle dict and measurement names.
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#TODO: make them the same so they can be indexed the same.
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if '1' in pname:
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t_initial = self.cycle_times[self.measure_cycles["read1_{0}".format(port)]]
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t_final = self.cycle_times[self.measure_cycles["read1_{0}".format(port)]+1]
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t_initial = self.cycle_times[self.measure_cycles[port]["read1"]]
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t_final = self.cycle_times[self.measure_cycles[port]["read1"]+1]
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elif '0' in pname:
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t_initial = self.cycle_times[self.measure_cycles["read0_{0}".format(port)]]
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t_final = self.cycle_times[self.measure_cycles["read0_{0}".format(port)]+1]
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t_initial = self.cycle_times[self.measure_cycles[port]["read0"]]
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t_final = self.cycle_times[self.measure_cycles[port]["read0"]+1]
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self.stim.gen_meas_power(meas_name="{0}{1}".format(pname, port),
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t_initial=t_initial,
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t_final=t_final)
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@ -271,11 +268,11 @@ class delay(simulation):
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for pname in self.power_meas_names:
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if "write" not in pname:
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continue
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t_initial = self.cycle_times[self.measure_cycles["write0_{0}".format(port)]]
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t_final = self.cycle_times[self.measure_cycles["write0_{0}".format(port)]+1]
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t_initial = self.cycle_times[self.measure_cycles[port]["write0"]]
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t_final = self.cycle_times[self.measure_cycles[port]["write0"]+1]
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if '1' in pname:
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t_initial = self.cycle_times[self.measure_cycles["write1_{0}".format(port)]]
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t_final = self.cycle_times[self.measure_cycles["write1_{0}".format(port)]+1]
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t_initial = self.cycle_times[self.measure_cycles[port]["write1"]]
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t_final = self.cycle_times[self.measure_cycles[port]["write1"]+1]
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self.stim.gen_meas_power(meas_name="{0}{1}".format(pname, port),
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t_initial=t_initial,
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@ -733,8 +730,7 @@ class delay(simulation):
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self.add_write("W data 0 address 11..11 to write value",
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self.probe_address,data_zeros,write_port)
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self.measure_cycles["write0_{0}".format(write_port)] = len(self.cycle_times)-1
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#self.write0_cycle=len(self.cycle_times)-1 # Remember for power measure
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self.measure_cycles[write_port]["write0"] = len(self.cycle_times)-1
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# This also ensures we will have a H->L transition on the next read
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self.add_read("R data 1 address 00..00 to set DOUT caps",
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@ -742,18 +738,14 @@ class delay(simulation):
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self.add_read("R data 0 address 11..11 to check W0 worked",
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self.probe_address,data_zeros,read_port)
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self.measure_cycles["read0_{0}".format(read_port)] = len(self.cycle_times)-1
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#self.read0_cycle=len(self.cycle_times)-1 # Remember for power measure
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self.measure_cycles[read_port]["read0"] = len(self.cycle_times)-1
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self.add_noop_all_ports("Idle cycle (if read takes >1 cycle)",
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inverse_address,data_zeros)
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#Does not seem like is is used anywhere commenting out for now.
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#self.idle_cycle=len(self.cycle_times)-1 # Remember for power measure
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self.add_write("W data 1 address 11..11 to write value",
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self.probe_address,data_ones,write_port)
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self.measure_cycles["write1_{0}".format(write_port)] = len(self.cycle_times)-1
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#self.write1_cycle=len(self.cycle_times)-1 # Remember for power measure
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self.measure_cycles[write_port]["write1"] = len(self.cycle_times)-1
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self.add_write("W data 0 address 00..00 to clear DIN caps",
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inverse_address,data_zeros,write_port)
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@ -764,8 +756,7 @@ class delay(simulation):
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self.add_read("R data 1 address 11..11 to check W1 worked",
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self.probe_address,data_zeros,read_port)
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self.measure_cycles["read1_{0}".format(read_port)] = len(self.cycle_times)-1
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#self.read1_cycle=len(self.cycle_times)-1 # Remember for power measure
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self.measure_cycles[read_port]["read1"] = len(self.cycle_times)-1
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self.add_noop_all_ports("Idle cycle (if read takes >1 cycle))",
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self.probe_address,data_zeros)
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@ -780,7 +771,7 @@ class delay(simulation):
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def set_stimulus_variables(self):
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simulation.set_stimulus_variables(self)
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self.measure_cycles = {}
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self.measure_cycles = [{} for port in range(self.total_ports)]
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def create_test_cycles(self):
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"""Returns a list of key time-points [ns] of the waveform (each rising edge)
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@ -794,11 +785,10 @@ class delay(simulation):
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#Get any available read/write port in case only a single write or read ports is being characterized.
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cur_read_port = self.get_available_port(get_read_port=True)
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cur_write_port = self.get_available_port(get_read_port=False)
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debug.check(cur_read_port != None, "Characterizer requires at least 1 read port")
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debug.check(cur_write_port != None, "Characterizer requires at least 1 write port")
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#Characterizing the remaining target ports. Not the final design.
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#Create test cycles for specified target ports.
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write_pos = 0
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read_pos = 0
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while True:
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