mirror of https://github.com/VLSIDA/OpenRAM.git
Clean up code formatting.
This commit is contained in:
Matt Guthaus
parent
4e232c49ad
commit
ad7fe1be51
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@ -54,7 +54,9 @@ class precharge(pgate.pgate):
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self.add_pin_list(["bl", "br", "en", "vdd"])
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def add_ptx(self):
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"""Initializes the upper and lower pmos"""
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"""
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Initializes the upper and lower pmos
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"""
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self.pmos = ptx(width=self.ptx_width,
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tx_type="pmos")
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self.add_mod(self.pmos)
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@ -63,8 +65,10 @@ class precharge(pgate.pgate):
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def route_vdd_rail(self):
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"""
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Adds a vdd rail at the top of the cell
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"""
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"""Adds a vdd rail at the top of the cell"""
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# adds the rail across the width of the cell
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vdd_position = vector(0, self.height - self.m1_width)
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self.add_rect(layer="metal1",
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@ -77,7 +81,7 @@ class precharge(pgate.pgate):
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vdd_pos = vector(pmos_pin.cx(), vdd_position.y + 0.5*self.m1_width)
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self.add_path("metal1", [pmos_pin.uc(), vdd_pos])
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# Add the M1->M2->M3 stack at the left edge
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# Add the M1->M2->M3 stack
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vdd_contact_pos = vector(0.5*self.width, vdd_position.y + 0.5*self.m1_width)
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=vdd_contact_pos)
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@ -89,7 +93,9 @@ class precharge(pgate.pgate):
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def create_ptx(self):
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"""Create both the upper_pmos and lower_pmos to the module"""
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"""
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Create both the upper_pmos and lower_pmos to the module
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"""
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self.lower_pmos_inst=self.add_inst(name="lower_pmos",
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mod=self.pmos)
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@ -105,7 +111,9 @@ class precharge(pgate.pgate):
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def place_ptx(self):
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"""Place both the upper_pmos and lower_pmos to the module"""
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"""
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Place both the upper_pmos and lower_pmos to the module
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"""
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# Compute the other pmos2 location, but determining offset to overlap the
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# source and drain pins
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@ -126,7 +134,9 @@ class precharge(pgate.pgate):
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self.upper_pmos2_inst.place(upper_pmos2_pos)
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def connect_poly(self):
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"""Connects the upper and lower pmos together"""
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"""
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Connects the upper and lower pmos together
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"""
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offset = self.lower_pmos_inst.get_pin("G").ll()
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# connects the top and bottom pmos' gates together
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@ -145,7 +155,10 @@ class precharge(pgate.pgate):
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height=self.poly_width)
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def route_en(self):
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"""Adds the en input rail, en contact/vias, and connects to the pmos"""
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"""
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Adds the en input rail, en contact/vias, and connects to the pmos
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"""
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# adds the en contact to connect the gates to the en rail on metal1
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offset = self.lower_pmos_inst.get_pin("G").ul() + vector(0,0.5*self.poly_space)
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self.add_contact_center(layers=("poly", "contact", "metal1"),
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@ -160,7 +173,10 @@ class precharge(pgate.pgate):
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def place_nwell_and_contact(self):
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"""Adds a nwell tap to connect to the vdd rail"""
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"""
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Adds a nwell tap to connect to the vdd rail
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"""
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# adds the contact from active to metal1
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well_contact_pos = self.upper_pmos1_inst.get_pin("D").center().scale(1,0) \
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+ vector(0, self.upper_pmos1_inst.uy() + contact.well.height/2 + drc("well_extend_active"))
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@ -169,9 +185,10 @@ class precharge(pgate.pgate):
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implant_type="n",
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well_type="n")
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# leave an extra pitch for the height
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self.height = well_contact_pos.y + contact.well.height + self.m1_pitch
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# nwell should span the whole design since it is pmos only
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self.add_rect(layer="nwell",
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offset=vector(0,0),
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width=self.width,
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@ -179,7 +196,10 @@ class precharge(pgate.pgate):
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def route_bitlines(self):
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"""Adds both bit-line and bit-line-bar to the module"""
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"""
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Adds both bit-line and bit-line-bar to the module
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"""
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# adds the BL on metal 2
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offset = vector(self.bitcell.get_pin(self.bitcell_bl).cx(),0) - vector(0.5 * self.m2_width,0)
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self.bl_pin = self.add_layout_pin(text="bl",
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@ -197,6 +217,9 @@ class precharge(pgate.pgate):
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height=self.height)
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def connect_to_bitlines(self):
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"""
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Connect the bitlines to the devices
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"""
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self.add_bitline_contacts()
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self.connect_pmos(self.lower_pmos_inst.get_pin("S"),self.get_pin("bl"))
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self.connect_pmos(self.lower_pmos_inst.get_pin("D"),self.get_pin("br"))
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@ -205,7 +228,9 @@ class precharge(pgate.pgate):
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def add_bitline_contacts(self):
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"""Adds contacts/via from metal1 to metal2 for bit-lines"""
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"""
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Adds contacts/via from metal1 to metal2 for bit-lines
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"""
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stack=("metal1", "via1", "metal2")
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upper_y = self.upper_pmos1_inst.get_pin("S").cy()
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@ -221,7 +246,9 @@ class precharge(pgate.pgate):
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offset = vector(self.br_pin.cx(), lower_y))
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def connect_pmos(self, pmos_pin, bit_pin):
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""" Connect pmos pin to bitline pin """
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"""
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Connect a pmos pin to bitline pin
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"""
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left_pos = vector(min(pmos_pin.cx(),bit_pin.cx()), pmos_pin.cy())
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right_pos = vector(max(pmos_pin.cx(),bit_pin.cx()), pmos_pin.cy())
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